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* ARMV7: S5P: rename from s5pc1xx to s5pMinkyu Kang2010-08-23-22/+28
| | | | | | | | Because of these are common files around s5p Socs, rename from s5pc1xx to s5p. And getting cpu_id is SoC specific, so move to SoC's header file. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* ARMV7: S5P: make s5p-common for sharing the code between s5pc1xx and s5pc2xxMinkyu Kang2010-08-23-2/+46
| | | | | | | | This patch adds basic support for s5pc210. s5p-common will be used by all of s5p SoCs. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* S5P: Use accessor functions instead of SoC specific defines to access the ↵Minkyu Kang2010-08-17-29/+44
| | | | | | | | | | | base address This patch is intended to prepare the other S5P SoC. (s5pc210) If use SoC specific defines then can't share with other SoC. So, make the accessor functions for access the base address by common way. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* Merge branch 'master' of git://git.denx.de/u-boot-samsungWolfgang Denk2010-08-04-0/+73
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| * S5P: support mmc driverMinkyu Kang2010-08-03-0/+73
| | | | | | | | | | | | | | | | This patch adds support mmc driver for s5p SoC Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* | Merge branch 'master' of /home/wd/git/u-boot/masterWolfgang Denk2010-08-03-96/+570
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| * | cmd_usage(): simplify return code handlingWolfgang Denk2010-07-24-26/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lots of code use this construct: cmd_usage(cmdtp); return 1; Change cmd_usage() let it return 1 - then we can replace all these ocurrances by return cmd_usage(cmdtp); This fixes a few places with incorrect return code handling, too. Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2010-07-24-5/+341
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| | * | ppc4xx: Add ECC status info to machine-check exception for IBM DDR2 coreStefan Roese2010-07-23-0/+16
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Add "ecctest" command to test/simulate ECC errorsStefan Roese2010-07-23-0/+287
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the "ecctest" command to test and simulate ECC errors (single bit and/or double bit) while running from SDRAM. Currently only the IBM DDR2 controller is supported (405EX, 440SP(e), 460EX/GT). This is done by copying and calling functions, modifying the SDRAM controller operation mode, in internal SRAM/OCM. For correctable ECC errors (single bit) only the status will be printed since the DDR2 controller doesn't provide the faulting address: => ecctest 1000000 1 Using address 01000000 for 1 bit ECC error injection ECC: Correctable error Uncorrectable ECC errors (double bit) will also display the faulting address: => ecctest 1000000 2 Using address 01000000 for 2 bit ECC error injection ECC: Uncorrectable error at 0x0001000000 To enable this "ecctest" function you need to define CONFIG_CMD_ECCTEST in the board config header. Tested on katmai and t3corp. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: DDR/ECC: Use correct macros to clear error statusStefan Roese2010-07-23-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the correct macro instead of the hardcoded 0x4c to clear the ECC status in the 440/460 DDR(2) error status register after ECC initialization. Also the non-440 parts (405EX(r) right now) and the IBM DDR PPC variants (440GX) use a different registers to clear this error status. Use the correct ones. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Only define DDR2 registers for the correct PowerPC variantsStefan Roese2010-07-23-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure that some SDRAM/DDR2 registers are only defined for the PPC variants really implementing those registers. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Add CONFIG_DDR_RFDC_FIXED to allow board specific RFDC valuesStefan Roese2010-07-23-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using this define, a board can define an opimized RFDC value and use the auto calibration code to "tune" the remaining DDR2 controller calibration register. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | powerpc/85xx: Rework P1022 SERDES is_serdes_configured supportKumar Gala2010-07-21-11/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move serdes init until after we are in ram so we can keep track of a global static protocal map for the particular serdes config we are in. This makes is_serdes_configured() much simplier and not constantly reading registers to determine if a given device is enabled based on the protocol. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/85xx: Rework MPC8536 SERDES is_serdes_configured supportKumar Gala2010-07-21-40/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move serdes init until after we are in ram so we can keep track of a global static protocal map for the particular serdes config we are in. This makes is_serdes_configured() much simplier and not constantly reading registers to determine if a given device is enabled based on the protocol. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/p3041: Add various p3041 related definesKumar Gala2010-07-20-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p3041 to cpu_type_list and SVR list * Added number of LAWs for p3041 * Set CONFIG_MAX_CPUS to 4 for p3041 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/p5020: Add various p5020 related defines (and p5010)Kumar Gala2010-07-20-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p5020 & p5010 to cpu_type_list and SVR list * Added number of LAWs for p5020 * Set CONFIG_MAX_CPUS to 2 for p5020 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/mpc85xx: Report FMAN # to match user manualEmil Medve2010-07-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The user manual refers to FMAN1 and FMAN2 not 0 and 1. Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/p4080: Add setting of clock-frequency for clockgen nodeKumar Gala2010-07-20-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On QorIQ CoreNet based devices we have a global clocking block. We want to keep track of SYSCLK frequency as it is what is used to derive all other frequencies in the SoC Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/85xx: Use fdt_node_offset_by_compat_reg for clock-frequency updatesKumar Gala2010-07-20-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move to using fdt_node_offset_by_compat_reg to find the node offsets we want to update instead of using aliases. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliasesKumar Gala2010-07-20-3/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we used an alias the pci node to determine which node to fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to find the node to update. Additionally, we replace the code in each board with a single macro call that makes assumes uniform naming and reduces duplication in this area. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/86xx: Move PCI/PCIe address defines into common immap_86xx.hKumar Gala2010-07-20-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove dupliacted setting of PCI/PCIe address and offsets in board config.h. Renamed CONFIG_SYS_PCI1/2_ADDR to CONFIG_SYS_PCI1/2ADDR on MPC8641 boards since its really PCIE controllers and not PCI. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.hKumar Gala2010-07-20-0/+20
| |/ / | | | | | | | | | | | | | | | | | | Remove dupliacted setting of PCI/PCIe address and offsets in board config.h. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | Drop support for GTH boardWolfgang Denk2010-07-17-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board maintainer states: The GTH board is obsolete and has not been manufactured for several years. To my knowledge, no recent U-Boot build has been tested on that card. So drop support for this board. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Thomas Lange <thomas@corelatus.se> Acked-by: Thomas Lange<thomas@corelatus.se>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tiWolfgang Denk2010-07-16-1/+96
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| * | ARMV7: Add basic gpmc initialization for OMAP4Steve Sakoman2010-07-15-1/+96
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds a gpmc_init function for OMAP4 and adds calls to gpmc_init for existing OMAP4 boards: panda and sdp4430 Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2010-07-16-516/+751
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| * | | powerpc/85xx: Move p1022ds slot code into board fileKumar Gala2010-07-16-70/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code to map SERDES configs to slot names is board specific and not chip specific. Thus it should live in board/freescale/p1022ds/ and not in arch/powerpc/cpu/. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/85xx: Add command to report errata workaroundsKumar Gala2010-07-16-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 'errata' command to report what errata we workaround. Report workaround for erratum SATA-A001 on P1022/P1013. Also sorted the CONFIG_CMD_* list. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc: add support for the Freescale P1022DS reference boardTimur Tabi2010-07-16-0/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specifics: 1) 36-bit only 2) Booting from NOR flash only 3) Environment stored in NOR flash only 4) No SPI support 5) No DIU support Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | fsl: add LAW target to fsl_pci_info structureTimur Tabi2010-07-16-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the LAW target (enum law_trgt_if) to the fsl_pci_info structure, so that we can capture the LAW target for a given PCI or PCIE controller. Also update the SET_STD_PCI_INFO and SET_STD_PCIE_INFO macros to assign the LAW_TRGT_IF_PCI[E]_x macro to the LAW target field of the structure. This will allow future PCI[E] code to configure the LAW target automatically, rather than requiring each board to it for each PCI controller separately. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/85xx: Add support for link stack & STAC on e5500Kumar Gala2010-07-16-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The e5500 has a link register stack and segment target address cache. Its safe to enable these bits on older e500 cores as the bits are implemented in the register. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/85xx: Add recognition of e5500 coreKumar Gala2010-07-16-10/+18
| | | | | | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc 83xx/85xx: Merge lbc upmconfig codeBecky Bruce2010-07-16-127/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each platform had its own version of the upmconfig, despite the init process being identical. Now that we have a spot for common lbc code, create a common upmconfig() there. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | mpc85xx: Add reginfo commandBecky Bruce2010-07-16-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new command dumps the TLBCAM, the LAWs, and the BR/OR regs. Add CONFIG_CMD_REGINFO to the config for all MPC85xx parts. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | drivers/misc/fsl_law.c: Rearrange code to avoid duplicationBecky Bruce2010-07-16-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code redefines functions based on FSL_CORENET_ vs not - create macros/inlines instead that hide the differences. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | mpc85xx: Add print_tlbcam() functionBecky Bruce2010-07-16-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This dumps out the contents of TLB1 on 85xx-based systems. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | mpc85xx: tlb.c cleanupsBecky Bruce2010-07-16-26/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extract the operation to read a tlb into a function - we will need this later to print out the tlbs, and there's no point in duplicating the code. Create a TSIZE_TO_BYTES macro to deal with the conversion from the MAS field to an actual size instead of duplicating this in code. There are a few misc other minor cleanups. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | 83xx/85xx/86xx: LBC register cleanupBecky Bruce2010-07-16-339/+196
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/8xxx: Add is_core_disabled to remove disabled cores from dtbKumar Gala2010-07-16-7/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If we explicitly disabled a core remove it from the dtb we pass on to the kernel. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | mpc8xxx: Remove cpu-handles for cpus we deleteKumar Gala2010-07-16-6/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We may have cpu-handles pointing to the cpu nodes we delete. If so we should delete the handles as well. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/8xxx: Add base support for the SEC4Kim Phillips2010-07-16-1/+47
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/8xxx: Distinguish between incompatible SEC h/w typesKim Phillips2010-07-16-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_FSL_SEC_COMPAT is set to 2 for the SEC 2.x and SEC 3.x. Parts with newer SEC h/w versions will increment the number to accomodate incompatible code changes. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | fdt: move fsl specific code from common fdt area to mpc8xxx/fdt.cKim Phillips2010-07-16-3/+137
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-pxaWolfgang Denk2010-07-15-7/+451
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| * | | | PXA: Add support for LMS285GF05 into pxafbMarek Vasut2010-07-14-0/+34
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
| * | | | Voipac PXA270 LCD SupportMarek Vasut2010-07-14-0/+33
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
| * | | | PXA: Add OneNAND booting support to start.SMarek Vasut2010-07-14-5/+43
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
| * | | | PXA: Add PWM2 and PWM3 regs to pxa-regs.hMarek Vasut2010-07-14-1/+9
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
| * | | | PXA: Add hardware init helper macrosMarek Vasut2010-07-14-0/+324
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds macros for the following purposes: - GPIO configuration - SDRAM configuration - Wakeup - Clock configuration - Interrupt controller configuration These macros are intended to replace numerous copies of the same code. Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
generated by cgit v1.1 at 2024-12-26 04:53:32 +0000