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authorStefan Roese <sr@denx.de>2010-07-21 19:06:26 +0200
committerStefan Roese <sr@denx.de>2010-07-23 09:55:03 +0200
commitbe24ef6e8ee48602f453bf16c7b7b708fac0eb2f (patch)
treeb2faf421c0c945f809d9509b137eeb7fc77e1df1 /arch
parent58eb869ffc45856658648e24a88d47fdd3768b53 (diff)
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ppc4xx: Add ECC status info to machine-check exception for IBM DDR2 core
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/cpu/ppc4xx/traps.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/traps.c b/arch/powerpc/cpu/ppc4xx/traps.c
index 1616772..b5562ad 100644
--- a/arch/powerpc/cpu/ppc4xx/traps.c
+++ b/arch/powerpc/cpu/ppc4xx/traps.c
@@ -209,6 +209,22 @@ MachineCheckException(struct pt_regs *regs)
/* Clear MCSR */
mtspr(SPRN_MCSR, val);
}
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
+ /*
+ * Read and print ECC status register/info:
+ * The faulting address is only known upon uncorrectable ECC
+ * errors.
+ */
+ mfsdram(SDRAM_ECCES, val);
+ if (val & SDRAM_ECCES_CE)
+ printf("ECC: Correctable error\n");
+ if (val & SDRAM_ECCES_UE) {
+ printf("ECC: Uncorrectable error at 0x%02x%08x\n",
+ mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL));
+ }
+#endif /* CONFIG_DDR_ECC ... */
+
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
mfsdram(DDR0_00, val) ;
printf("DDR0: DDR0_00 %lx\n", val);