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* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2010-07-04-53/+107
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| * ppc4xx: Cleanup Boot/FLASH TLB reassignment for PPC440/460Stefan Roese2010-07-01-15/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Background Info: Some PPC440/460 boards have caches enabled in the Boot/FLASH TLB (via init.S) to speed up the boot process. In relocate_code (start.S) the cache inhibit attribute for this TLB is set to disable cache. This is needed for the CFI FLASH driver. This patch now cleans this code up: - CONFIG_SYS_TLB_FOR_BOOT_FLASH is defined to 0 (default TLB) if not defined in the top of this file. This way, we can remove an ugly #ifdef in this code. - Replace complex "#if defined(CONFIG_440EP) || defined(CONFIG_GR)..." statement with "#if defined(CONFIG_440)". - Remove unnecessary cache invalidate calls resulting in faster bootup. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add DDR1/2 macros in ppc4xx-sdram.h for non-405EX as wellStefan Roese2010-07-01-1/+3
| | | | | | | | | | | | | | This patch adds some DDR(2) macros to all PPC4xx's equipped with this IBM DDR1/2 controller. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: DDR2: Complete RDSS configuration on non-SPD based boardsStefan Roese2010-07-01-14/+38
| | | | | | | | | | | | | | | | | | As described in item #10 of the SDRAM initialization (chapter 22.2.9 of the PPC460EX/EXr/GT users manual), RDSS may need to be adjusted. The code for this is now factored out and executed for non-SPD based boards as well. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Enable overwriting of default scan window for IBM DDR2 controllerStefan Roese2010-07-01-12/+10
| | | | | | | | | | | | | | | | | | | | | | This patch makes it possible to overwrite the default auto-calibration scan window (SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR] values) with board specific values. The parameters of the weak default function are corrected as well. This way we don't need the casts any more. This feature will be used by an upcoming PPC460GT board port. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Enable PCIe support without PCI support on PPC440/460Stefan Roese2010-07-01-1/+11
| | | | | | | | | | | | | | | | | | | | | | By not defining CONFIG_SYS_PCI_MASTER_INIT and CONFIG_SYS_PCI_TARGET_INIT, PCI support (host and adapter) will not be enabled. But it's still possible to use the U-Boot PCI infrastructure for the PCIe ports. This configuration option is needed for a new 460GT board, which uses PCIe but has PCI disabled. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Enable booting with Option E on 460EX/EXr/GTStefan Roese2010-07-01-10/+39
| | | | | | | | | | | | | | | | | | This patch enables booting with option E on the PPC460EX/EXr/GT. When booting with Option E, the PLL is in bypass, CPR0_PLLC[ENG]=0. The Software Boot Configuration Procedure is needed to engage the PLL and perform a chip reset. Signed-off-by: Stefan Roese <sr@denx.de>
* | USB OHCI support for at91sam9g45 SoCSergey Matyukevich2010-06-30-2/+12
|/ | | | | | | | | | Add USB OHCI support for at91sam9g45ekes/at91sam9m10g45ek boards. Note that according to errata from Atmel, OHCI is not operational on the first revision of at91sam9g45 chip. So this patch enables OHCI support for later revisions. Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
* Merge branch 'master' into nextWolfgang Denk2010-06-30-9/+12
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| * MPC512x: workaround data corruption for unaligned local bus accessesWolfgang Denk2010-06-29-9/+12
| | | | | | | | | | | | | | | | | | | | | | Commit 460c2ce3 "MPC5200: workaround data corruption for unaligned local bus accesses" fixed the problem for MPC5200 only, but MPC512x is affected as well, so apply the same fix here, too. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: Detlev Zundel <dzu@denx.de>
* | powerpc/bootcount: Add bootcount support for MPC512xMichael Weiss2010-06-29-0/+5
| | | | | | | | | | | | | | This also uses the breadcrumb register as on MPC5200. Signed-off-by: Michael Weiss <michael.weiss@ifm.com> Signed-off-by: Detlev Zundel <dzu@denx.de>
* | avr32: add unaligned.hAndreas Bießmann2010-06-29-0/+1
| | | | | | | | | | | | | | | | | | This patch fixes following error: zlib.c:31:27: error: asm/unaligned.h: No such file or directory Suggested-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
* | avr32: disable branch foldingAndreas Bießmann2010-06-29-3/+4
| | | | | | | | | | | | | | | | Due to a hardware bug mentioned in latest AP7000 datasheet errata (revision M from 09.09) branch folding is unreliable. This patch disables CPUCR.FE bitfield as stated in datasheet. Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
* | Fix (null) problem for AVR32 boardsReinhard Meyer (-VC)2010-06-29-2/+3
| | | | | | | | | | | | | | | | | | | | Currently the U-Boot address ranges for AVR32 boards are printed like this: "U-Boot code: (null) -> 0001183c data: 000188e8 -> 0004e9b0" This patch fixes this to print: "U-Boot code: 00000000 -> 0001183c data: 000188f8 -> 0004e9c0" Signed-off-by: Reinhard Meyer <info@emk-elektronik.de>
* | Merge branch 'next' of git://git.denx.de/u-boot-ti into nextWolfgang Denk2010-06-29-1/+1
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| * | DaVinci: EMAC: Get EMAC_MDIO_PHY_NUM from config filesPrakash PM2010-06-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently EMAC_MDIO_PHY_NUM is defined as 1 in emac_defs.h. Because of this, EMAC does not work on EVMs which do not have phy connected at 1. Moving the macro to board config file makes this configurable depending on where the phy is connected on the MDIO bus. This patch fixes the board reset issue observed during network access on DM365EVM. EMAC driver was assuming EMAC_MDIO_PHY_NUM as 1 but it is 0 on DM365EVM. This patch is verified on da830/omap-l137, dm365 and dm644x evms. Signed-off-by: Prakash PM <prakash.pm@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-sh into nextWolfgang Denk2010-06-29-5/+46
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| * | | sh: Add trigger_address_error and support cpu resetNobuhiro Iwamatsu2010-06-28-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This add support cpu reset by trigger_address_error function. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | sh: Fix path of irqflags.hNobuhiro Iwamatsu2010-06-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This changes path of irqflags.h from linux/ to asm/. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | sh: Fix overflow problem in get_ticksNobuhiro Iwamatsu2010-06-28-2/+18
| | |/ | |/| | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | Remove AmigaOneG3SE boardWolfgang Denk2010-06-23-27/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AmigaOneG3SE board has been orphaned or a very long time, and broken for more than 12 releases resp. more than 3 years. As nobody seems to be interested any more in this stuff we may as well ged rid of it, especially as it clutters many areas of the code so it is a continuous pain for all kinds of ongoing work. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | Get rid of bogus CONFIG_SYS_BUS_HZ and CONFIG_SYS_CONFIG_BUS_CLK definitionsWolfgang Denk2010-06-23-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_BUS_HZ has not really been used anywhere except to be redined as CONFIG_SYS_BUS_CLK; in addition, the mpc7448hpc2 had the bogus CONFIG_SYS_CONFIG_BUS_CLK setting which duplicated the funtionality. Change all this to use CONFIG_SYS_BUS_CLK consistently. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Frank Gottschling <fgottschling@eltec.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Cc: Eran Man <eran@nbase.co.il> Cc: Stefan Roese <sr@denx.de> Cc: Nye Liu <nyet@zumanetworks.com> Cc: Roy Zang <tie-fei.zang@freescale.com>
* | | Merge branch 'master' into nextWolfgang Denk2010-06-23-131/+184
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| * Prepare v2010.06-rc3v2010.06-rc3Wolfgang Denk2010-06-23-70/+70
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * MPC5200: workaround data corruption for unaligned local bus accessesWolfgang Denk2010-06-23-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC5200 has a nasty problem that will cause silent data corruption when performing unaligned 16 or 32 byte accesses when reading from the local bus - typically this affects reading from flash. The problem can be easily shown: => md fc0c0000 10 fc0c0000: 323e4337 01626f6f 74636d64 3d72756e 2>C7.bootcmd=run fc0c0010: 206e6574 5f6e6673 00626f6f 7464656c net_nfs.bootdel fc0c0020: 61793d35 00626175 64726174 653d3131 ay=5.baudrate=11 fc0c0030: 35323030 00707265 626f6f74 3d656368 5200.preboot=ech => md fc0c0001 10 fc0c0001: 65636801 00000074 0000003d 00000020 ech....t...=... fc0c0011: 0000005f 00000000 00000074 00000061 ..._.......t...a fc0c0021: 00000000 00000064 00000065 00000035 .......d...e...5 fc0c0031: 00000000 00000062 0000003d 0000006f .......b...=...o => md.w fc0c0001 10 fc0c0001: 0000 3701 0000 6f74 0000 643d 0000 6e20 ..7...ot..d=..n fc0c0011: 0000 745f 0000 7300 0000 6f74 0000 6c61 ..t_..s...ot..la This commit implements a workaround at least for the most blatant problem: using memcpy() from NOR flash. We rename the assembler routine into __memcpy() and provide a wrapper, which will use a byte-wise copy loop for unaligned source or target addresses when reading from NOR flash, and branch to the optimized __memcpy() in all other cases, thus minimizing the performance impact. Tested on lite5200b and TQM5200S. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
| * ARM: remove unused VIDEOLFB ATAGMinkyu Kang2010-06-23-40/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | ATAG_VIDEOLFB is not used anywhere. The belowing warning is occurred due to this ATAG. [ 0.000000] Ignoring unrecognised tag 0x54410008 This patch fixed it. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Martin Krause <Martin.Krause@tqs.de>
| * Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2010-06-22-4/+4
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| | * Fix wrong orion5x MPP and GIPO writel argumentsAlbert Aribaud2010-06-22-4/+4
| | | | | | | | | | | | | | | | | | | | | Orion5x MPP and GPIO setting code had writel arguments the wrong way around. Fixed and tested. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
| * | ARM: fix bug in macro __arch_ioremap.Terry Lv2010-06-22-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Terry Lv <r65388@freescale.com> Fix commit message and code formatting. Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | ARM: Align stack to 8 bytesVitaly Kuzmichev2010-06-22-6/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM ABI requires that the stack be aligned to 8 bytes as it is noted in Procedure Call Standard for the ARM Architecture: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042d/index.html Unaligned SP also causes the problem with variable-length arrays allocation when VLA address becomes less than stack pointer during aligning of this address, so the next 'push' in the stack overwrites first 4 bytes of VLA. Signed-off-by: Vitaly Kuzmichev <vkuzmichev@mvista.com> Tested on tx25(mx25), imx27lite(mx27), qong(mx31) and trab(s3c2400) Tested-by: Wolfgang Denk <wd@denx.de>
| * | arch/arm/cpu/arm_cortexa8/omap3/cache.S: make build with older toolsWolfgang Denk2010-06-18-4/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The push / pop instructions used in this file are available only with more recent tool chains: cache.S: Assembler messages: cache.S:133: Error: bad instruction `push {r0,r1,r2,lr}' cache.S:160: Error: bad instruction `pop {r1,r2,r3,pc}' cache.S:164: Error: bad instruction `push {r0,r1,r2,lr}' cache.S:191: Error: bad instruction `pop {r1,r2,r3,pc}' Change push/pop into stmfd/ldmfd instructions to support older versions of binutils as well. I verified that the modified source code generates exactly the same binary code. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Tom Rix <tom@bumblecow.com>
* | Merge branch 'master' into nextWolfgang Denk2010-06-18-191/+3595
|\ \ | |/ | | | | | | | | | | Conflicts: Makefile Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Merge branch 'fix' of git://git.denx.de/u-boot-pxaWolfgang Denk2010-06-17-1/+4
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| | * PXA: Align stack to 8 bytesMarek Vasut2010-06-13-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Part of this patch is by: Mikhail Kshevetskiy. Stack must be aligned to 8 bytes on PXA (possibly all armv5te) for LDRD/STRD instructions. In case LDRD/STRD is issued on an unaligned address, the behaviour is undefined. The issue was observed when working with the NAND code, which was rendered disfunctional. Also, the vsprintf() function had serious problems with printing 64bit wide long longs. After aligning the stack, this wrong behaviour is no longer present. Tested on: Marvell Littleton PXA310 board Toradex Colibri PXA320 board Aeronix Zipit Z2 PXA270 handheld Voipac PXA270 board Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-marvellWolfgang Denk2010-06-17-0/+1175
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| | * | Initial support for Marvell Orion5x SoCAlbert Aribaud2010-06-17-0/+1175
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the Marvell Orion5x SoC. It has no use alone, and must be followed by a patch to add Orion5x support for serial, then support for the ED Mini V2, an Orion5x-based product from LaCie. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-tiWolfgang Denk2010-06-17-0/+1
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: CONFLICT (rename/add): Rename board/davinci/da830evm/Makefile->board/ti/tnetv107xevm/Makefile in 89b765c7f6ddfde07ba673dd4adbeb5da391a81b. board/ti/tnetv107xevm/Makefile added in HEAD But files were identical, so no problem. Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * | | TI: DaVinci: Add board specific code for da850 EVMSudhakar Rajashekhara2010-06-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provides initial support for TI OMAP-L138/DA850 SoC devices on a Logic PD EVM board. Provides: Initial boot and configuration. Support for i2c. UART support (console). Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Acked-by: Ben Gardiner <bengardiner@nanometrics.ca> Reviewed-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| | * | | AM35x: Add support for EMIF4Vaibhav Hiremath2010-06-07-0/+273
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the EMIF4 interface available in the AM35x processors. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| | * | | omap3: Consolidate SDRC related operationsVaibhav Hiremath2010-06-07-168/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consolidated SDRC related functions into one file - sdrc.c And also replaced sdrc_init with generic memory init function (mem_init), this generalization of omap memory setup is necessary to support the new emif4 interface introduced in AM3517. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| | * | | omap3: Calculate CS1 size only when SDRC isVaibhav Hiremath2010-06-07-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | initialized for CS1 From: Vaibhav Hiremath <hvaibhav@ti.com> The patch makes sure that size for SDRC CS1 gets calculated only when the CS1 SDRC is initialized. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| | * | | ARM1176: TI: TNETV107X soc initial supportCyril Chemparathy2010-06-07-0/+1872
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a bunch on on-chip integrated peripherals. This is an initial commit with basic functionality, more commits with drivers, etc. to follow. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| | * | | ARM1176: Coexist with other ARM1176 platformsCyril Chemparathy2010-06-07-21/+47
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ARM1176 CPU specific code is too specific to the SMDK6400 architecture. The following changes were necessary prerequisites for the addition of other SoCs based on ARM1176. Existing board's (SMDK6400) configuration has been modified to keep behavior unchanged despite these changes. 1. Peripheral port remap configurability The earlier code had hardcoded remap values specific to s3c64xx in start.S. This change makes the peripheral port remap addresses and sizes configurable. 2. U-Boot code relocation support Most architectures allow u-boot code to run initially at a different address (possibly in NOR) and then get relocated to its final resting place in RAM. Added support for this capability in ARM1176 architecture. 3. Disable TCM if necessary If a ROM based bootloader happened to have initialized TCM, we disable it here to keep things sane. 4. Remove unnecessary SoC specific includes ARM1176 code does not really need this SoC specific include. The presence of this include prevents builds on other ARM1176 archs. 5. Modified virt-to-phys conversion during MMU disable The original MMU disable code masks out too many bits from the load address when it tries to figure out the physical address of the jump target label. Consequently, it ends up branching to the wrong address after disabling the MMU. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-06-17-190/+2415
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| | * AM35x: Add support for EMIF4Vaibhav Hiremath2010-06-08-0/+273
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the EMIF4 interface available in the AM35x processors. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| | * omap3: Consolidate SDRC related operationsVaibhav Hiremath2010-06-08-168/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consolidated SDRC related functions into one file - sdrc.c And also replaced sdrc_init with generic memory init function (mem_init), this generalization of omap memory setup is necessary to support the new emif4 interface introduced in AM3517. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| | * omap3: Calculate CS1 size only when SDRC isVaibhav Hiremath2010-06-08-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | initialized for CS1 From: Vaibhav Hiremath <hvaibhav@ti.com> The patch makes sure that size for SDRC CS1 gets calculated only when the CS1 SDRC is initialized. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| | * ARM1176: TI: TNETV107X soc initial supportCyril Chemparathy2010-06-08-0/+1872
| | | | | | | | | | | | | | | | | | | | | | | | | | | TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a bunch on on-chip integrated peripherals. This is an initial commit with basic functionality, more commits with drivers, etc. to follow. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| | * ARM1176: Coexist with other ARM1176 platformsCyril Chemparathy2010-06-08-21/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ARM1176 CPU specific code is too specific to the SMDK6400 architecture. The following changes were necessary prerequisites for the addition of other SoCs based on ARM1176. Existing board's (SMDK6400) configuration has been modified to keep behavior unchanged despite these changes. 1. Peripheral port remap configurability The earlier code had hardcoded remap values specific to s3c64xx in start.S. This change makes the peripheral port remap addresses and sizes configurable. 2. U-Boot code relocation support Most architectures allow u-boot code to run initially at a different address (possibly in NOR) and then get relocated to its final resting place in RAM. Added support for this capability in ARM1176 architecture. 3. Disable TCM if necessary If a ROM based bootloader happened to have initialized TCM, we disable it here to keep things sane. 4. Remove unnecessary SoC specific includes ARM1176 code does not really need this SoC specific include. The presence of this include prevents builds on other ARM1176 archs. 5. Modified virt-to-phys conversion during MMU disable The original MMU disable code masks out too many bits from the load address when it tries to figure out the physical address of the jump target label. Consequently, it ends up branching to the wrong address after disabling the MMU. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| | * ARM1136: Fix cache_flush() error and correct cpu_init_crit() commentsGeorge G. Davis2010-06-01-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" instruction which means "Invalidate Both Caches" when in fact the intent is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7, c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate Both Caches" instruction to insure that memory is consistent with any dirty cache lines. Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so that they correctly describe the actual ARM1136 CP15 C7 Cache Operations used. Signed-off-by: George G. Davis <gdavis@mvista.com>
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