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| * | x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to KconfigBin Meng2015-01-13-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig options so that we can remove them from board configuration file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | x86: Allow a hardcoded TSC frequency provided by KconfigBin Meng2015-01-13-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default U-Boot automatically calibrates TSC running frequency via MSR and PIT. The calibration may not work on every x86 processor, so a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to allow bypassing the calibration and assign a hardcoded TSC frequency CONFIG_TSC_FREQ_IN_MHZ. Normally the bypass should be turned on in a simulation environment like qemu. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | x86: coreboot: Set up timer base correctlyBin Meng2015-01-13-13/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value of base_time in coreboot's timestamp table as our timer base, otherwise TSC counter value will be used. Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS, the value of base_time in the timestamp table is still zero, so we must exclude this case too (this is currently seen on booting coreboot in qemu). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | x86: fsp: Drop get_hob_type() and get_hob_length()Bin Meng2015-01-13-44/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These two are not worth having separate inline functions as they are really simple, so drop them. Also changed 'type' parameter of fsp_get_next_hob() from u16 to uint. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | x86: Add an 'mtrr' command to list and adjust MTRRsSimon Glass2015-01-13-0/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to be able to see the MTRR setup in U-Boot. Add a command to list the state of the variable MTRR registers and allow them to be changed. Update the documentation to list some of the available commands. This does not support fixed MTRRs as yet. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: ivybridge: Update microcode early in bootSimon Glass2015-01-13-13/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the normal update (which happens much later) does not work. This seems to have something to do with the 'no eviction' mode in the CAR, or at least moving the microcode update after that causes it not to work. For now, do an update early on so that it definitely works. Also refuse to continue unless the microcode update check (later in boot) is successful. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Disable CAR before relocation on platforms that need itSimon Glass2015-01-13-0/+8
| | | | | | | | | | | | | | | | | | | | | For platforms with CAR we should disable it before relocation. Check if this function is available and call it if so. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Add a way to turn off the CARSimon Glass2015-01-13-0/+46
| | | | | | | | | | | | | | | | | | | | | Cache-as-RAM should be turned off when we relocate since we want to run from RAM. Add a function to perform this task. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Commit the current MTRRs before relocationSimon Glass2015-01-13-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Once we stop running from ROM we should set up the MTTRs to speed up execution. This is only needed for platforms that don't have an FSP. Also in the Coreboot case, the MTRRs are set up for us. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Request MTRRs for DRAM regionsSimon Glass2015-01-13-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | We should use MTRRs to speed up execution. Add a list of MTRR requests which will dealt with when we relocate and run from RAM. We set RAM as cacheable (with write-back) and registers as non-cacheable. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Set up an MTRR for the video frame bufferSimon Glass2015-01-13-0/+7
| | | | | | | | | | | | | | | | | | | | | Set the frame buffer to write-combining. This makes it faster, although for scrolling write-through is even faster for U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add support for MTRRsSimon Glass2015-01-13-101/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Memory Type Range Registers are used to tell the CPU whether memory is cacheable and if so the cache write mode to use. Clean up the existing header file to follow style, and remove the unneeded code. These can speed up booting so should be supported. Add these to global_data so they can be requested while booting. We will apply the changes during relocation (in a later commit). Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Drop support for ROM cachingSimon Glass2015-01-13-25/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Tidy up VESA mode numbersSimon Glass2015-01-13-4/+7
| | | | | | | | | | | | | | | | | | | | | There are some bits which should be ignored when displaying the mode number. Make sure that they are not included in the mode that is displayed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Use cache, don't clear the display in video BIOSSimon Glass2015-01-13-3/+2
| | | | | | | | | | | | | | | | | | | | | There is no need to run with the cache disabled, and there is no point in clearing the display frame buffer since U-Boot does it later. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Only run the Video BIOS when video is enabledSimon Glass2015-01-13-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This takes about about 700ms on link when running natively and 900ms when running using the emulator. It is a waste of time if video is not enabled, so don't bother running the video BIOS in that case. We could add a command to run the video BIOS later when needed, but this is not considered at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Drop RAMTOP KconfigSimon Glass2015-01-13-12/+0
| | | | | | | | | | | | | | | | | | | | | We don't need this in U-Boot since we calculate it based on available memory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Correct XIP_ROM_SIZESimon Glass2015-01-13-1/+1
| | | | | | | | | | | | | | | | | | | | | This should default to the size of the ROM for faster execution before relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: crownbay: Add pci devices in the dts fileBin Meng2015-01-13-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton 1/2/3/4). Add the corresponding device nodes in the crownbay.dts per Open Firmware PCI bus bindings. Also a comment block is added for the 'stdout-path' property in the chosen node, mentioning that by default the legacy superio serial port (io addr 0x3f8) is still used on Crown Bay as the console port. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | x86: Use ePAPR defined properties for x86-uartBin Meng2015-01-13-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use ePAPR defined properties for x86-uart: clock-frequency and current-speed. Assign the value of clock-frequency in device tree to plat->clock of x86-uart instead of using hardcoded number. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | x86: Simplify the fsp hob access functionsBin Meng2015-01-12-100/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the troublesome union hob_pointers so that some annoying casts are no longer needed in those hob access routines. This also improves the readability. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | pci: Make pci apis usable before relocationBin Meng2015-01-12-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a gd->hose to save the pci hose in the early phase so that apis in drivers/pci/pci.c can be used before relocation. Architecture codes need assign a valid gd->hose in the early phase. Some variables are declared as static so change them to be either stack variable or global data member so that they can be used before relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which just affects some print format. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | x86: Support pci bus scan in the early phaseBin Meng2015-01-12-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | On x86, some peripherals on pci buses need to be accessed in the early phase (eg: pci uart) with a valid pci memory/io address, thus scan the pci bus and do the corresponding resource allocation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.cBin Meng2015-01-12-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | arch/x86/cpu/pci.c has access to the U-Boot global data thus DECLARE_GLOBAL_DATA_PTR is needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | x86: Clean up the board dts filesBin Meng2015-01-12-24/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commits cleans up the board dts files. - Correct the serial port register size to 8 - Remove the misleading status = "disabled" statement in the serial.dtsi - Move the inclusion of skeleton.dtsi from serial.dtsi to board dts files - Let the board dts file define stdout-path in the chosen node - Remove device nodes in board dts files thar are duplicated to skeleton.dtsi Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | x86: Rename coreboot.dsti to serial.dtsiBin Meng2015-01-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The name of coreboot.dtsi is misleading, as it actually describes the legacy serial port device node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | x86: Remove alex.dts in arch/x86/dtsBin Meng2015-01-12-25/+0
| |/ | | | | | | | | | | | | No board is using alex.dts, so remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | ppc4xx: remove some CPCI405 variantsMatthias Fuchs2015-01-13-9/+0
| | | | | | | | | | | | only keep CPCI4052 Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | ppc4xx: remove G2000 boardMatthias Fuchs2015-01-13-4/+0
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | ppc4xx: remove WUH405 boardMatthias Fuchs2015-01-13-4/+0
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | ppc4xx: remove VOH405 boardMatthias Fuchs2015-01-13-4/+0
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | ppc4xx: remove PMC405 boardMatthias Fuchs2015-01-13-4/+0
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | ppc4xx: remove PCI405 boardMatthias Fuchs2015-01-13-4/+0
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | ppc4xx: remove OCRTC boardMatthias Fuchs2015-01-13-4/+0
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | ppc4xx: remove HUB405 boardMatthias Fuchs2015-01-13-4/+0
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | ppc4xx: remove HH405 boardMatthias Fuchs2015-01-13-4/+0
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | ppc4xx: remove DU440 boardMatthias Fuchs2015-01-13-4/+0
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | ppc4xx: remove DU405 boardMatthias Fuchs2015-01-13-4/+0
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | ppc4xx: remove DP405 boardMatthias Fuchs2015-01-13-4/+0
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | ppc4xx: remove CPCIISER4 boardMatthias Fuchs2015-01-13-4/+0
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | ppc4xx: remove CMS700 boardMatthias Fuchs2015-01-13-4/+0
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | ppc4xx: remove ASH405 boardMatthias Fuchs2015-01-13-4/+0
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | ppc4xx: remove AR405 boardMatthias Fuchs2015-01-13-4/+0
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | ppx4xx: remove APC405 boardMatthias Fuchs2015-01-13-4/+0
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | m68k: remove TASREG boardMatthias Fuchs2015-01-13-4/+0
|/ | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Acked-by: Stefan Roese <sr@denx.de>
* arc: introduce "mdbtrick" targetAlexey Brodkin2015-01-09-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MetaWare debugger (MDB) is still used as a primary tool for interaction with target via JTAG. Moreover some very advanced features are not yet implemented in GDB for ARC (and not sure if they will be implemnted sometime soon given complexity and rare need for those features for common user). So if we're talking about development process when U-Boot is loaded in target memory not by low-level boot-loader but manually through JTAG chances are high developer uses MDB for it. But MDB doesn't support PIE (position-independent executable) - it will refuse to even start - that means no chance to load elf contents on target. Then the only way to load U-Boot in MDB is to fake it by: 1. Reset PIE flag in ELF header This is simpe - on attempt to open elf MDB checks header and if it doesn't match its expectation refuces to use provided elf. 2. Strip all debug information from elf If (1) is done then MDB will open elf but on parsing of elf's debug info it will refuse to process due to debug info it cannot understand (symbols with PIE relocation). Even though it could be done manually (I got it documented quite a while ago here http://www.denx.de/wiki/U-Boot/ARCNotes) having this automated way is very convenient. User may build U-Boot that will be loaded on target via MDB saying "make mdbtrick". Then if we now apply the manipulation MDB will happily start and will load all required sections into the target. Indeed there will be no source-level debug info available. But still MDB will do its work on showing disassembly, global symbols, registers, accessing low-level debug facilities etc. As a summary - this is a pretty dirty hack but it simplifies life a lot for us ARc developers. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de>
* arm: build arch memset/memcpy in Thumb2 modeStefan Agner2015-01-09-87/+142
| | | | | | | | | | | | | | | | | | | | | | Resynchronize memcpy/memset with kernel 3.17 and build them in Thumb2 mode (unified syntax). Those assembler files can be built and linked in ARM mode too, however when calling them from Thumb2 built code, the stack got corrupted and the copy did not succeed (the exact details have not been traced back). However, the Linux kernel builds those files in Thumb2 mode. Hence U-Boot should build them in Thumb2 mode too when CONFIG_SYS_THUMB_BUILD is set. To build the files without warning, some assembler instructions had to be replaced with their UAL compliant variant (thanks Jeroen for this input). To build the file in Thumb2 mode the implicit-it=always option need to be set to generate Thumb2 compliant IT instructions where needed. We add this option to the general AFLAGS when building for Thumb2. Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Agner <stefan@agner.ch>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-01-08-5/+5
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| * dt: socfpga: Replace num-chipselect with num-csMarek Vasut2015-01-07-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This optional DT property is called 'num-cs', so repair the misnomers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssiMarek Vasut2015-01-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
generated by cgit v1.1 at 2024-10-17 03:32:42 +0000