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| author | Bin Meng <bmeng.cn@gmail.com> | 2014-12-30 22:53:20 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-01-12 17:03:41 -0800 |
| commit | fa5530b85dd48e58700188754ee852444466bf28 (patch) | |
| tree | cc20bd27dc02eafaf6eb3ad49900019473b61563 /arch | |
| parent | 4722c035cf0f7f82633af9d5fe19d4336805e800 (diff) | |
| download | u-boot-imx-fa5530b85dd48e58700188754ee852444466bf28.zip u-boot-imx-fa5530b85dd48e58700188754ee852444466bf28.tar.gz u-boot-imx-fa5530b85dd48e58700188754ee852444466bf28.tar.bz2 | |
x86: Support pci bus scan in the early phase
On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/cpu/pci.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index 404fbb6..1eee08b 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -29,6 +29,7 @@ int pci_early_init_hose(struct pci_controller **hosep) board_pci_setup_hose(hose); pci_setup_type1(hose); + hose->last_busno = pci_hose_scan(hose); gd->arch.hose = hose; *hosep = hose; |