summaryrefslogtreecommitdiff
path: root/arch/x86
Commit message (Expand)AuthorAgeLines
* x86: Remove legacy pci codesBin Meng2015-11-13-71/+0
* x86: qemu: Convert to use driver model pciBin Meng2015-11-13-50/+0
* x86: qemu: Move chipset-specific codes from pci.c to qemu.cBin Meng2015-11-13-72/+82
* x86: qemu: Remove call to vgabios executionBin Meng2015-11-13-18/+1
* x86: queensbay: Really disable IGDBin Meng2015-11-13-10/+23
* x86: Move CONFIG_8259_PIC and CONFIG_8254_TIMER to KconfigBin Meng2015-11-13-0/+15
* x86: Rename pcat_ to i8254 and i8259 accordinglyBin Meng2015-11-13-8/+8
* x86: Initialize i8254 timer counter 1Bin Meng2015-11-13-0/+10
* x86: Fix cosmetic issues in the i8254 and i8259 codesBin Meng2015-11-13-53/+52
* x86: Remove dead codes wrapped by PARANOID_IRQ_TRIGGERSBin Meng2015-11-13-16/+0
* x86: Rename CONFIG_SYS_NUM_IRQS to SYS_NUM_IRQSBin Meng2015-11-13-12/+10
* Various Makefiles: Add SPDX-License-Identifier tagsTom Rini2015-11-10-0/+4
* x86: Use the generic bitops headersFabio Estevam2015-11-05-1/+20
* x86: Add support for Advantech SOM-6896George McCollister2015-10-21-1/+45
* x86: ivybridge: Enable the MRC cacheBin Meng2015-10-21-8/+2
* x86: ivybridge: Measure the MRC code execution timeSimon Glass2015-10-21-0/+3
* x86: ivybridge: Fix car_uninit() to correctly set run stateSimon Glass2015-10-21-1/+1
* x86: ivybridge: Check the RTC return valueSimon Glass2015-10-21-3/+10
* x86: ivybridge: Use 'ret' instead of 'rcode'Simon Glass2015-10-21-8/+8
* x86: chromebook_link: Enable the debug UARTSimon Glass2015-10-21-0/+7
* x86: Init the debug UART if enabledSimon Glass2015-10-21-8/+3
* x86: Pass correct cpu_index to ap_init()Bin Meng2015-10-21-2/+2
* x86: galileo: Enable mrc cacheBin Meng2015-10-21-0/+4
* x86: quark: Implement mrc cacheBin Meng2015-10-21-7/+64
* x86: ivybridge: Correct two typos for MRCBin Meng2015-10-21-2/+2
* x86: Remove unused rw-mrc-cache properties in the link and panther dts filesBin Meng2015-10-21-5/+0
* x86: baytrail: Issue full system reset in reset_cpu()Bin Meng2015-10-21-0/+6
* x86: Enable mrc cache for bayleybay and minnowmaxBin Meng2015-10-21-0/+12
* x86: baytrail: Save mrc cache to spi flashBin Meng2015-10-21-0/+19
* x86: fsp: Pass mrc cache to fsp_init() and save it to gd after fsp_init()Bin Meng2015-10-21-1/+35
* x86: Use struct mrc_region to describe a mrc regionBin Meng2015-10-21-15/+27
* x86: ivybridge: Use APIs provided in the mrccache libBin Meng2015-10-21-108/+4
* x86: Add more common routines to manipulate mrc cacheBin Meng2015-10-21-0/+140
* x86: Add various minor tidy-ups in mrccache codesBin Meng2015-10-21-18/+16
* x86: Do sanity test on the cache record in mrccache_update()Bin Meng2015-10-21-1/+4
* x86: Move mrccache.[c|h] to a common placeBin Meng2015-10-21-4/+3
* x86: Add ENABLE_MRC_CACHE Kconfig optionBin Meng2015-10-21-0/+8
* x86: fsp: Add a hdr sub-command to show header informationBin Meng2015-10-21-1/+31
* x86: fsp: Make hob command a sub-command to fspBin Meng2015-10-21-7/+28
* x86: fsp: Print GUID whenever applicable in the hob command outputBin Meng2015-10-21-3/+19
* x86: fsp: Compact the output of hob commandBin Meng2015-10-21-14/+14
* x86: Add SMBIOS table supportBin Meng2015-10-21-0/+522
* x86: Move install_e820_map() out of zimage.cBin Meng2015-10-21-29/+41
* x86: Initialize GDT entry 1 to be the 32-bit CS as wellBin Meng2015-10-21-1/+6
* x86: Allow disabling IGD on Intel QueensbayBin Meng2015-10-21-0/+32
* x86: ivybridge: Remove the dead codes that programs pci bridgeBin Meng2015-10-21-32/+0
* x86: fsp: Report correct number of E820 table entriesBin Meng2015-09-28-1/+2
* x86: quark: Configure MTRR to enable cacheBin Meng2015-09-16-0/+111
* x86: galileo: Add PCIe root port IRQ routingBin Meng2015-09-16-0/+12
* x86: quark: Initialize thermal sensor properlyBin Meng2015-09-16-0/+54
generated by cgit v1.1 at 2024-11-10 15:43:40 +0000