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* x86: Check PIRQ routing table sanity in the F segmentBin Meng2015-04-29-5/+13
| | | | | | | | | | Previously the PIRQ routing table sanity check was performed against the original table provided by the platform codes. Now we switch to check its sanity on the final table in the F segment as this one is the one seen by the OS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: minnowmax: add GPIO banks in the device treeGabriel Huau2015-04-29-0/+42
| | | | | | | | | | There are 6 banks: 4 banks for CORE: available in S0 mode 2 banks for SUS (Suspend): available in S0-S5 mode Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: fix the GPIOBASE addressGabriel Huau2015-04-29-1/+1
| | | | | | | | The correct GPIOBASE address on the baytrail is 0x48 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Implement PIRQ routingBin Meng2015-04-29-4/+440
| | | | | | | | Implement Intel Queensbay platform-specific PIRQ routing support. The chipset PIRQ routing setup is called in the arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Support platform PIRQ routingBin Meng2015-04-29-0/+300
| | | | | | | | | | | | | | | On x86 boards, platform chipset receives up to four different interrupt signals from PCI devices (INTA/B/C/D), which in turn will be routed to chipset internal PIRQ lines then routed to 8259 PIC finally if configuring the whole system to work under the so-called PIC mode (in contrast to symmetric IO mode which uses IOAPIC). We add two major APIs to aid this, one for routing PIRQ and the other one for generating a PIRQ routing table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Write configuration tables in last_stage_init()Bin Meng2015-04-29-0/+90
| | | | | | | | We can write the configuration table in last_stage_init() for all x86 boards, but not with coreboot since coreboot already has them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add a function to assign IRQ numbers to PCI deviceBin Meng2015-04-29-0/+35
| | | | | | | | | Add a function to assign an IRQ number to PCI device's interrupt line register in its configuration space, so that the PCI device can have its interrupt working under PIC mode after OS boots up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Install a default e820 table in the __weak install_e820_map()Bin Meng2015-04-29-7/+22
| | | | | | | | Create a default e820 table with 3 entries which is enough to boot a Linux kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Clean up arch/x86/include/asm/e820.hBin Meng2015-04-29-131/+2
| | | | | | | There are lots of unused codes defined in e820.h, clean it up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add alias for SPI node in the board dtsBin Meng2015-04-29-2/+11
| | | | | | | | | Since Intel ICH SPI driver has been converted to driver model, we need add an alias for SPI node in the board dts files otherwise SPI flash won't be detected due to 'invalid bus' error. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Set serial port IRQ for SMSC LPC47MBin Meng2015-04-29-0/+3
| | | | | | | | | For starting a Linux console on the superio serial port under interrupt mode, the IRQ number must be configured. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Avoid using PCH prefixBin Meng2015-04-29-4/+3
| | | | | | | | | | The prefix PCH was taken from ivybridge port. However Queensbay platform official document does not mention PCH. It is composed of TunnelCreek processor and Topcliff IOH chipset. For accuracy, avoid using PCH prefix in the macro. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Remove the old VGA driverBin Meng2015-04-29-206/+0
| | | | | | | CONFIG_VIDEO_VGA is no longer needed thus remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* sandbox: Move CONFIG_SYS_VSNPRINTF to KconfigSimon Glass2015-04-18-0/+3
| | | | | | Move this over to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* Kconfig: Move CONFIG_BOOTSTAGE to KconfigSimon Glass2015-04-18-1/+10
| | | | | | | Move CONFIG_BOOT_STAGE and its associated options to Kconfig. Adjust existing users and code. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: select CONFIG_DM* optionsMasahiro Yamada2015-04-18-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As mentioned in the previous commit, adding default values in each Kconfig causes problems because it does not co-exist with the "depends on" syntax. (Please note this is not a bug of Kconfig.) We should not do so unless we have a special reason. Actually, for CONFIG_DM*, we have no good reason to do so. Generally, CONFIG_DM is not a user-configurable option. Once we convert a driver into Driver Model, the board only works with Driver Model, i.e. CONFIG_DM must be always enabled for that board. So, using "select DM" is more suitable rather than allowing users to modify it. Another good thing is, Kconfig warns unmet dependencies for "select" syntax, so we easily notice bugs. Actually, CONFIG_DM and other related options have been added without consistency: some into arch/*/Kconfig, some into board/*/Kconfig, and some into configs/*_defconfig. This commit prefers "select" and cleans up the following issues. [1] Never use "CONFIG_DM=n" in defconfig files It is really rare to add "CONFIG_FOO=n" to disable CONFIG options. It is more common to use "# CONFIG_FOO is not set". But here, we do not even have to do it. Less than half of OMAP3 boards have been converted to Driver Model. Adding the default values to arch/arm/cpu/armv7/omap3/Kconfig is weird. Instead, add "select DM" only to appropriate boards, which eventually eliminates "CONFIG_DM=n", etc. [2] Delete redundant CONFIGs Sandbox sets CONFIG_DM in arch/sandbox/Kconfig and defines it again in configs/sandbox_defconfig. Likewise, OMAP3 sets CONFIG_DM arch/arm/cpu/armv7/omap3/Kconfig and defines it also in omap3_beagle_defconfig and devkit8000_defconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* x86: chromebook_link: dts: Add PCH and LPC devicesSimon Glass2015-04-18-33/+52
| | | | | | | | | | | | The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: Add a uclass for an Low Pin Count (LPC) deviceSimon Glass2015-04-18-0/+29
| | | | | | | | | On x86 systems this device is commonly used to provide legacy port access. It is sort-of a replacement for the old ISA bus. Add a uclass for this, and allow it to have child devices. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: Add a uclass for a Platform Controller HubSimon Glass2015-04-18-9/+29
| | | | | | | | | Add a simple uclass for this chip which is often found in x86 systems where the CPU is a separate device. The device can have children, so make it scan the device tree for these. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: spi: Convert ICH SPI driver to driver modelSimon Glass2015-04-18-20/+25
| | | | | | | | | | | | Convert this driver over to use driver model. Since all x86 platforms use it, move x86 to use driver model for SPI and SPI flash. Adjust all dependent code and remove the old x86 spi_init() function. Note that this does not make full use of the new PCI uclass as yet. We still scan the bus looking for the device. It should move to finding its details in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: pci: Convert chromebook_link to use driver model for pciSimon Glass2015-04-18-67/+59
| | | | | | | | | | | | | | | | Move chromebook_link over to driver model for PCI. This involves: - adding a uclass for platform controller hub - removing most of the existing PCI driver - adjusting how CPU init works to use driver model instead - rename the lpc compatible string (it will be removed later) This does not really take advantage of driver model fully, but it does work. Furture work will improve the code structure to remove many of the explicit calls to init the board. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: pci: Convert coreboot to use driver model for pciSimon Glass2015-04-18-47/+23
| | | | | | Move coreboot-x86 over to driver model for PCI. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: pci: Add a PCI driver for driver modelSimon Glass2015-04-18-0/+50
| | | | | | | Add a simple x86 PCI driver which uses standard functions provided by the architecture. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Split up arch_cpu_init()Simon Glass2015-04-16-0/+8
| | | | | | | | At present we do more in this function than we should. Split out the post-driver-model part into a separate function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a x86_ prefix to the x86-specific PCI functionsSimon Glass2015-04-16-187/+191
| | | | | | | | | | | | These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add support for panther (Asus Chromebox)Simon Glass2015-04-16-0/+81
| | | | | | | | | | | | | | | | | | | | Support running U-Boot as a coreboot payload. Tested peripherals include: - Video (HDMI and DisplayPort) - SATA disk - Gigabit Ethernet - SPI flash USB3 does not work. This may be a problem with the USB3 PCI driver or something in the USB3 stack and has not been investigated So far this is disabled. The SD card slot also does not work. For video, coreboot will need to run the OPROM to set this up. With this board, bare support (running without coreboot) is not available as yet. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Support machines with >4GB of RAMSimon Glass2015-04-16-2/+4
| | | | | | | | | | | | | Some systems have more than 4GB of RAM. U-Boot can only place things below 4GB so any memory above that should not be used. Ignore any such memory so that the memory size will not exceed the maximum. This prevents gd->ram_size exceeding 4GB which causes problems for PCI devices which use DMA. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* malloc_f: enable SYS_MALLOC_F by default if DM is onMasahiro Yamada2015-03-28-3/+0
| | | | | | | | | | | | | | This option has a bool type, not hex. Fix it and enable it if CONFIG_DM is on because Driver Model always requires malloc memory. Devices are scanned twice, before/after relocation. CONFIG_SYS_MALLOC_F should be enabled to use malloc memory before relocation. As it is board-independent, handle it globally. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Robert Baldyga <r.baldyga@samsung.com>
* generic-board: select SYS_GENERIC_BOARD for some architecturesMasahiro Yamada2015-03-28-1/+0
| | | | | | | | | | | | We have done with the generic board conversion for all the boards of ARC, Blackfin, M68000, MicroBlaze, MIPS, NIOS2, Sandbox, X86. Let's select SYS_GENERIC_BOARD for those architectures, so we can tell which architecture has finished the conversion at a glance. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
* generic-board: move __HAVE_ARCH_GENERIC_BOARD to KconfigMasahiro Yamada2015-03-28-3/+0
| | | | | | | | Move the option to Kconfig renaming it to CONFIG_HAVE_GENERIC_BOARD. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
* x86: quark: Enable on-chip ethernet controllersBin Meng2015-03-24-0/+19
| | | | | | | | | | Intel Quark SoC integrates two 10/100 ethernet controllers which can be connected to an external RMII PHY. The MAC IP is from Designware. Enable this support with the existing U-Boot Designware MAC driver so that the ethernet port on Intel Galileo board can be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* arch/x86/cpu/quark/mrc.c: Switch to U_BOOT_DATE / U_BOOT_TIMETom Rini2015-03-24-1/+2
| | | | | | | | | | | Using __DATE__ and __TIME__ results in an error due to -Werror=date-time with gcc-4.9 (__DATE__ / __TIME__ might prevent reproducible builds) so switch these over to U_BOOT_DATE / U_BOOT_TIME Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: MRC codes clean upBin Meng2015-03-24-1049/+955
| | | | | | | | | | | | This patch cleans up the quark MRC codes coding style by: - Remove BIT0/1../31 defines from mrc_util.h - Create names for the documented BITs and use them - For undocumented single BITs, use (1 << n) directly - For undocumented ORed BITs, use the hex number directly - Remove redundancy parenthesis all over the codes - Replace to use lower case hex numbers Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* remove unnecessary version.h includesRob Herring2015-03-24-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
* dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to KconfigSimon Glass2015-02-12-0/+6
| | | | | Move this option to Kconfig and update all boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: Move driver model CONFIGs to KconfigSimon Glass2015-02-12-0/+9
| | | | | | | Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2015-02-10-149/+10646
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| * x86: Use tab instead of space to indent in PCIE_ECAM_BASEBin Meng2015-02-06-1/+1
| | | | | | | | | | | | | | | | Space is used before 'default' in PCIE_ECAM_BASE in arch/x86/Kconfig so it looks misaligned. Replace the space with tab to indent. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add SD/MMC support to quark/galileoBin Meng2015-02-06-0/+11
| | | | | | | | | | | | | | | | Intel Galileo board has a microSD slot which is routed from Quark SoC SDIO controller. Enable SD/MMC support so that we can use an SD card. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add SPI support to quark/galileoBin Meng2015-02-06-0/+30
| | | | | | | | | | | | | | | | | | | | The Quark SoC contains a legacy SPI controller in the legacy bridge which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS control register offset in the ICH SPI driver is wrong for the Quark SoC too, unprotect_spi_flash() is added to enable the flash write. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: galileo: Add GPIO supportBin Meng2015-02-06-0/+14
| | | | | | | | | | | | | | | | | | | | Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31), which is just the same one found in other x86 chipset. Since we programmed the GPIO register block base address, we should be able to enable the GPIO support on Intel Galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Initialize non-standard BARsBin Meng2015-02-06-0/+78
| | | | | | | | | | | | | | | | | | Quark SoC has some non-standard BARs (excluding PCI standard BARs) which need be initialized with suggested values. This includes GPIO, WDT, RCBA, PCIe ECAM and some ACPI register block base addresses. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Call MRC in dram_init()Bin Meng2015-02-06-2/+122
| | | | | | | | | | | | | | | | Now that we have added Quark MRC codes, call MRC in dram_init() so that DRAM can be initialized on a Quark based board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Enable the Memory Reference Code buildBin Meng2015-02-06-0/+1
| | | | | | | | | | | | | | Turn on the Memory Reference code build in the quark Makefile. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add System Memory Controller supportBin Meng2015-02-06-0/+3210
| | | | | | | | | | | | | | The codes are actually doing the memory initialization stuff. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add utility codes needed for MRCBin Meng2015-02-06-0/+2068
| | | | | | | | | | | | | | Add various utility codes needed for Quark MRC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add Memory Reference Code (MRC) main routinesBin Meng2015-02-06-0/+391
| | | | | | | | | | | | | | Add the main routines for Quark Memory Reference Code (MRC). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Bypass TSC calibrationBin Meng2015-02-06-0/+5
| | | | | | | | | | | | | | | | | | For some unknown reason, the TSC calibration via PIT does not work on Quark. Enable bypassing TSC calibration and override TSC_FREQ_IN_MHZ to 400 per Quark datasheet in the Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Allow overriding TSC_FREQ_IN_MHZBin Meng2015-02-06-20/+20
| | | | | | | | | | | | | | | | We should allow the value of TSC_FREQ_IN_MHZ to be overridden by the one in arch/cpu/<xxx>/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Enable the Intel quark/galileo buildBin Meng2015-02-06-0/+18
| | | | | | | | | | | | | | | | | | Make the Intel quark/galileo support avaiable in Kconfig and Makefile. With this patch, we can generate u-boot.rom for Intel galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-09 22:34:30 +0000