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* x86: Add support for Advantech SOM-6896George McCollister2015-10-21-1/+45
| | | | | | | | | | | | | | | Advantech SOM-6896 is a Broadwell U based COM Express Compact Module Type 6. This patch adds support for it as a coreboot payload. On board SATA and SPI are functional. On board Ethernet isn't functional but since it's optional and ties up a PCIe x4 that is otherwise brought out, this isn't a concern at the moment. USB doesn't work since the xHCI driver appears to be broken. Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* x86: ivybridge: Enable the MRC cacheBin Meng2015-10-21-8/+2
| | | | | | | | | This works correctly now, so enable it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Dropped malloc() and adjusted commit message: Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Measure the MRC code execution timeSimon Glass2015-10-21-0/+3
| | | | | | | | This code takes about 450ms without the MRC cache and about 27ms with the cache. Add a debug timer so that this time can be displayed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Fix car_uninit() to correctly set run stateSimon Glass2015-10-21-1/+1
| | | | | | | | At present a missing $ causes this code to hang when using the MRC cache/ Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Check the RTC return valueSimon Glass2015-10-21-3/+10
| | | | | | | The RTC can fail, so check the return value for reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use 'ret' instead of 'rcode'Simon Glass2015-10-21-8/+8
| | | | | | | For consistency, use 'ret' to handle a return value. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: chromebook_link: Enable the debug UARTSimon Glass2015-10-21-0/+7
| | | | | | | Add support for the debug UART on link. This is useful for early debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Init the debug UART if enabledSimon Glass2015-10-21-8/+3
| | | | | | | | | If the debug UART is enabled, get it ready for use at the earliest possible opportunity. This is not actually very early, but until we have a stack it is difficult to make it work. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Pass correct cpu_index to ap_init()Bin Meng2015-10-21-2/+2
| | | | | | | | In sipi_vector.S, cpu_index (passed as %eax) is wrongly overwritten by the ap_init() function address. Correct it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: galileo: Enable mrc cacheBin Meng2015-10-21-0/+4
| | | | | | | | Now that we have added MRC cache on quark support codes, enable it on Intel Galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Implement mrc cacheBin Meng2015-10-21-7/+64
| | | | | | | | Using existing mrccache library to implement mrc cache support for Intel Quark. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Correct two typos for MRCBin Meng2015-10-21-2/+2
| | | | | | | It should be MRC, not MCR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Remove unused rw-mrc-cache properties in the link and panther dts filesBin Meng2015-10-21-5/+0
| | | | | | | | | "type" and "wipe-value" are never used by the mrccache codes. Remove them to avoid confusion. This also removes the alignment comment in the panther dts file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Issue full system reset in reset_cpu()Bin Meng2015-10-21-0/+6
| | | | | | | | | | | | | | | | | | | With MRC cache enabled, when typing 'reset' in the U-Boot shell, BayTrail FSP initialization hangs at "Configuring Memory Start": Setting BootMode to 0 Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56 Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE About to call MrcInit(); BayleyBay Platform Type CurrentMrcData.BootMode = 4 Taking Fastboot path! Configuring Memory Start... Changing reset_cpu() to do a full system reset fixes this issue. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Enable mrc cache for bayleybay and minnowmaxBin Meng2015-10-21-0/+12
| | | | | | | | | | | | Now that we have added MRC cache for Intel FSP and BayTrail codes, enable it for all BayTrail boards (Bayley Bay and Minnow Max). Note it turns out that FSP for Intel Atom E6xx does not produce the HOB for NV storage, so we don't have such functionality on Intel Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Save mrc cache to spi flashBin Meng2015-10-21-0/+19
| | | | | | | Save MRC cache to SPI flash in arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Pass mrc cache to fsp_init() and save it to gd after fsp_init()Bin Meng2015-10-21-1/+35
| | | | | | | | | | fsp_init() call has a parameter nvs_buf which is used by FSP as the MRC cache but currently is blindly set to NULL. Retreive the MRC cache from SPI flash and pass it to fsp_init() call. After the call, save FSP produced MRC cache to SPI flash too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Use struct mrc_region to describe a mrc regionBin Meng2015-10-21-15/+27
| | | | | | | | | | | | | | | | Currently struct fmap_entry is used to describe a mrc region. However this structure contains some other fields that are not related to mrc cache and causes confusion. Besides, it does not include a base address field to store SPI flash's base address. Instead in the mrccache.c it tries to use CONFIG_ROM_SIZE to calculate the SPI flash base address, which unfortunately is not 100% correct as CONFIG_ROM_SIZE may not match the whole SPI flash size. Define a new struct mrc_region and use it instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Use APIs provided in the mrccache libBin Meng2015-10-21-108/+4
| | | | | | | | Remove the call to custom mrc cache APIs, and use the ones provided in the mrccache lib. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add more common routines to manipulate mrc cacheBin Meng2015-10-21-0/+140
| | | | | | | | | | | | | | This adds mrccache_reserve(), mrccache_get_region() and mrccache_save() APIs to the mrccache codes. They are ported from the ivybridge implementation, but with some changes. For example, in the mrccache_reserve(), ivybridge version only reserves the pure MRC data, which causes additional malloc() when saving the cache as the save API needs some meta data. Now we change it to save the whole MRC date plus the meta data to elinimate the need for the malloc() later. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add various minor tidy-ups in mrccache codesBin Meng2015-10-21-18/+16
| | | | | | | | Fix some nits, improve some comments and reorder some codes a little bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Do sanity test on the cache record in mrccache_update()Bin Meng2015-10-21-1/+4
| | | | | | | | For the cache record to write in mrccache_update(), we should perform a sanity test to see if it is a valid one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move mrccache.[c|h] to a common placeBin Meng2015-10-21-4/+3
| | | | | | | | mrccache implementation can be common for all boards. Move it from ivybridge cpu directory to the common lib directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add ENABLE_MRC_CACHE Kconfig optionBin Meng2015-10-21-0/+8
| | | | | | | Create a Kconfig option for enabling MRC cache. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Add a hdr sub-command to show header informationBin Meng2015-10-21-1/+31
| | | | | | | | It would be helpful to have a command to show FSP header. So far it only supports FSP header which conforms to FSP spec 1.0. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Make hob command a sub-command to fspBin Meng2015-10-21-7/+28
| | | | | | | | | Introduce a new fsp command and make the existing hob command a sub-command to fsp for future extension. Also move cmd_hob.c to the dedicated fsp sub-directory in arch/x86/lib. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Print GUID whenever applicable in the hob command outputBin Meng2015-10-21-3/+19
| | | | | | | | When examining a HOB, it's useful to see which GUID this HOB belongs to. Add GUID output in the hob command to aid this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Compact the output of hob commandBin Meng2015-10-21-14/+14
| | | | | | | | Compact hob command output, especially by making hob type string a little bit shorter so that we can leave room for future extension. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add SMBIOS table supportBin Meng2015-10-21-0/+522
| | | | | | | | | | | | System Management BIOS (SMBIOS) is a specification for how motherboard and system vendors present management information about their products in a standard format by extending the BIOS interface on Intel architecture systems. As of today the latest spec is 3.0 and can be downloaded from DMTF website. This commit adds a simple and minimum required implementation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move install_e820_map() out of zimage.cBin Meng2015-10-21-29/+41
| | | | | | | | install_e820_map() has nothing to do with zimage related codes. Move it to a dedicated place. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Initialize GDT entry 1 to be the 32-bit CS as wellBin Meng2015-10-21-1/+6
| | | | | | | | Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
* x86: Allow disabling IGD on Intel QueensbayBin Meng2015-10-21-0/+32
| | | | | | | | | | Add a Kconfig option to disable the Integrated Graphics Device (IGD) so that it does not show in the PCI configuration space as a VGA disaplay controller. This gives a chance for U-Boot to run PCI/PCIe based graphics card's VGA BIOS and use that for the graphics console. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Remove the dead codes that programs pci bridgeBin Meng2015-10-21-32/+0
| | | | | | | Remove bd82x6x_pci_bus_enable_resources() that is not called anywhere. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Report correct number of E820 table entriesBin Meng2015-09-28-1/+2
| | | | | | | | | The logic to calculate the number of E820 table entries is wrong when walking through the FSP HOB tables. Fix it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jian Luo <jian.luo4@boschrexroth.de> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Configure MTRR to enable cacheBin Meng2015-09-16-0/+111
| | | | | | | | | | | | | | | | | Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs are accessed indirectly via the message port and not the traditional MSR mechanism. Only UC, WT and WB cache types are supported. We configure all the fixed range MTRRs with common values (VGA RAM as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as WB, which significantly improves the boot time performance. With this commit, it takes only 2 seconds for U-Boot to boot to shell on Intel Galileo board. Previously it took about 6 seconds. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: galileo: Add PCIe root port IRQ routingBin Meng2015-09-16-0/+12
| | | | | | | | Now we have enabled PCIe root port on Quark SoC, add its PIRQ routing information in the device tree as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Initialize thermal sensor properlyBin Meng2015-09-16-0/+54
| | | | | | | | | | | | | | Thermal sensor on Quark SoC needs to be properly initialized per Quark firmware writer guide, otherwise when booting Linux kernel, it triggers system shutdown because of wrong temperature in the thermal sensor is detected by the kernel driver (see below): [ 5.119819] thermal_sys: Critical temperature reached(206 C),shutting down [ 5.128997] Failed to start orderly shutdown: forcing the issue [ 5.135495] Emergency Sync complete Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Lock HMBOUND register before jumping to kernelBin Meng2015-09-16-0/+4
| | | | | | | | | | | | | | When Linux kernel boots, it hangs at: [ 0.829408] Intel Quark side-band driver registered This happens when Quark kernel Isolated Memory Region (IMR) driver tries to lock an IMR register to protect kernel's text and rodata sections. However in order to have IMR function correctly, HMBOUND register must be locked otherwise the system just hangs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Convert to use clrbits, setbits, clrsetbits macrosBin Meng2015-09-16-51/+21
| | | | | | | Change existing codes to use clrbits, setbits, clrsetbits macros. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Add clrbits, setbits, clrsetbits macros for message port accessBin Meng2015-09-16-0/+31
| | | | | | | | | On Intel Quark, lots of registers on the message port need be programmed. Add handy clrbits, setbits, clrsetbits macros for message port access. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: quark: Add PCIe/USB static register programming after memory initBin Meng2015-09-16-0/+86
| | | | | | | | | This adds static register programming for PCIe and USB after memory init as required by Quark firmware writer guide. Although not doing this did not cause any malfunction, just do it for safety. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Convert to use driver model eth on quark/galileoBin Meng2015-09-16-19/+0
| | | | | | | | Convert to use DM version of Designware ethernet driver on Intel quark/galileo. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Add USB PHY initialization supportBin Meng2015-09-09-0/+49
| | | | | | | | USB PHY needs to be properly initialized per Quark firmware writer guide, otherwise the EHCI controller on Quark SoC won't work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Convert to use driver model pci on quark/galileoBin Meng2015-09-09-78/+6
| | | | | | | Move to driver model pci for Intel quark/galileo. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Enable PCIe controller on quark/galileoBin Meng2015-09-09-0/+105
| | | | | | | | | | | | | Quark SoC holds the PCIe controller in reset following a power on. U-Boot needs to release the PCIe controller from reset. The PCIe controller (D23:F0/F1) will not be visible in PCI configuration space and any access to its PCI configuration registers will cause system hang while it is held in reset. Enable PCIe controller per Quark firmware writer guide. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Avoid chicken and egg problemBin Meng2015-09-09-15/+15
| | | | | | | | | | | | | | | | | | | | If we convert to use driver model pci on quark, we will encounter some chicken and egg problems like below: - To enable PCIe root ports, we need program some registers on the message bus via pci bus. With driver model, the first time to access pci bus, the pci enumeration process will be triggered. But without first enabling PCIe root ports, pci enumeration just hangs when scanning PCIe root ports. - Similar situation happens when trying to access GPIO from the PCIe enabling codes, as GPIO requires its block base address to be assigned via a pci configuration register in the bridge. To avoid such dilemma, replace all pci calls in the quark codes to use the local version which does not go through driver model. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Optimize MRC execution timeBin Meng2015-09-09-22/+57
| | | | | | | | | | | | | | | | | Intel Quark SoC has a low end x86 processor with only 400MHz frequency. Currently it takes about 15 seconds for U-Boot to boot to shell and the most time consuming part is with MRC, which is about 12 seconds. MRC programs lots of registers on the SoC internal message bus indirectly accessed via pci bus. To speed up the boot, create an optimized version of pci config read/write dword routines which directly operate on PCI I/O ports. These two routines are inlined to provide better performance too. Now it only takes about 3 seconds to finish MRC, which is really fast (4 times faster than before). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Convert to use more dm driversBin Meng2015-09-09-6/+0
| | | | | | | Move to driver model for RTC, USB and ETH on coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: panther: Add PCI and video configurationSimon Glass2015-09-09-0/+10
| | | | | | | | | Add a PCI node to the device tree. This allows SPI flash and SATA to work correctly. Also configure the video to come up correctly even though there is no keyboard. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* exynos: x86: dts: Add tpm nodes to the device tree for Chrome OS devicesSimon Glass2015-08-31-0/+10
| | | | | | | | | Add a TPM node to the various Chromebooks so that driver can be converted to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Christophe Ricard<christophe-h.ricard@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
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