summaryrefslogtreecommitdiff
path: root/arch/x86
Commit message (Expand)AuthorAgeLines
* x86: Add LAPIC setup codeSimon Glass2014-11-25-2/+181
* x86: Drop old CONFIG_INTEL_CORE_ARCH codeSimon Glass2014-11-25-28/+0
* x86: Refactor interrupt_init()Bin Meng2014-11-25-14/+23
* x86: Remove cpu_init_r() for x86Bin Meng2014-11-25-8/+0
* x86: Call cpu_init_interrupts() from interrupt_init()Bin Meng2014-11-25-2/+3
* x86: Add Intel speedstep and turbo mode codeSimon Glass2014-11-25-0/+219
* x86: ivybridge: Set up XHCI USBSimon Glass2014-11-25-0/+34
* x86: ivybridge: Set up EHCI USBSimon Glass2014-11-25-0/+33
* x86: dts: Add SATA settings for linkSimon Glass2014-11-25-0/+7
* x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+306
* x86: dts: Add LPC settings for linkSimon Glass2014-11-25-0/+8
* x86: dts: Move PCI peripherals into a pci nodeSimon Glass2014-11-25-13/+15
* x86: ivybridge: Add additional LPC initSimon Glass2014-11-25-1/+528
* x86: ivybridge: Add PCH initSimon Glass2014-11-25-0/+173
* x86: Add a simple header file for ACPISimon Glass2014-11-25-0/+24
* x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-25-0/+167
* x86: Set up edge triggering on interrupt 9Simon Glass2014-11-25-0/+49
* x86: pci: Add handlers before and after a PCI hose scanSimon Glass2014-11-25-0/+15
* x86: Add ioapic.h headerSimon Glass2014-11-25-0/+38
* x86: Factor out common values in the link scriptSimon Glass2014-11-25-7/+12
* x86: Ensure that all relocation data is included in the imageSimon Glass2014-11-25-1/+3
* x86: Panic if there is no relocation dataSimon Glass2014-11-25-0/+3
* x86: Remove board_early_init_r()Simon Glass2014-11-25-11/+0
* x86: Add ivybridge directory to MakefileSimon Glass2014-11-25-0/+2
* Merge git://git.denx.de/u-boot-x86Tom Rini2014-11-24-175/+6391
|\
| * x86: Rename chromebook-x86 to corebootSimon Glass2014-11-21-1/+1
| * x86: ivybridge: Implement SDRAM initSimon Glass2014-11-21-5/+1861
| * x86: ivybridge: Add LAPIC supportSimon Glass2014-11-21-0/+163
| * x86: Make show_boot_progress() commonSimon Glass2014-11-21-24/+24
| * x86: chromebook_link: Enable GPIO supportSimon Glass2014-11-21-0/+3
| * x86: ivybridge: Add support for early GPIO initSimon Glass2014-11-21-6/+158
| * x86: ivybridge: Add early init for PCH devicesSimon Glass2014-11-21-1/+524
| * x86: dts: Add microcode updates for ivybridge CPUSimon Glass2014-11-21-0/+1382
| * x86: ivybridge: Perform Intel microcode update on bootSimon Glass2014-11-21-0/+177
| * x86: ivybridge: Check BIST value on bootSimon Glass2014-11-21-0/+16
| * x86: ivybridge: Perform initial CPU setupSimon Glass2014-11-21-0/+274
| * x86: Add msr read/write functions that use a structureSimon Glass2014-11-21-0/+19
| * x86: Add clr/setbits functionsSimon Glass2014-11-21-0/+49
| * x86: Tidy up coreboot header usageSimon Glass2014-11-21-6/+6
| * x86: ivybridge: Add early LPC init so that serial worksSimon Glass2014-11-21-0/+110
| * x86: pci: Allow configuration before relocationSimon Glass2014-11-21-0/+63
| * x86: ivybridge: Enable PCI in early initSimon Glass2014-11-21-0/+67
| * x86: Support use of PCI before relocationSimon Glass2014-11-21-0/+31
| * x86: Refactor PCI to permit alternate initSimon Glass2014-11-21-15/+46
| * x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass2014-11-21-3/+311
| * x86: Emit post codes in startup code for ChromebooksSimon Glass2014-11-21-1/+38
| * x86: Build a .rom file which can be flashed to an x86 machineSimon Glass2014-11-21-0/+13
| * x86: Add chromebook_link boardSimon Glass2014-11-21-0/+298
| * x86: Allow timer calibration to work on ivybridgeSimon Glass2014-11-21-11/+21
| * x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directoryMasahiro Yamada2014-11-21-6/+6
generated by cgit v1.1 at 2024-11-09 20:46:01 +0000