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* x86: Use struct mrc_region to describe a mrc regionBin Meng2015-10-21-4/+9
| | | | | | | | | | | | | | | | Currently struct fmap_entry is used to describe a mrc region. However this structure contains some other fields that are not related to mrc cache and causes confusion. Besides, it does not include a base address field to store SPI flash's base address. Instead in the mrccache.c it tries to use CONFIG_ROM_SIZE to calculate the SPI flash base address, which unfortunately is not 100% correct as CONFIG_ROM_SIZE may not match the whole SPI flash size. Define a new struct mrc_region and use it instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add more common routines to manipulate mrc cacheBin Meng2015-10-21-0/+51
| | | | | | | | | | | | | | This adds mrccache_reserve(), mrccache_get_region() and mrccache_save() APIs to the mrccache codes. They are ported from the ivybridge implementation, but with some changes. For example, in the mrccache_reserve(), ivybridge version only reserves the pure MRC data, which causes additional malloc() when saving the cache as the save API needs some meta data. Now we change it to save the whole MRC date plus the meta data to elinimate the need for the malloc() later. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add various minor tidy-ups in mrccache codesBin Meng2015-10-21-10/+10
| | | | | | | | Fix some nits, improve some comments and reorder some codes a little bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Do sanity test on the cache record in mrccache_update()Bin Meng2015-10-21-1/+1
| | | | | | | | For the cache record to write in mrccache_update(), we should perform a sanity test to see if it is a valid one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move mrccache.[c|h] to a common placeBin Meng2015-10-21-0/+0
| | | | | | | | mrccache implementation can be common for all boards. Move it from ivybridge cpu directory to the common lib directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add SMBIOS table supportBin Meng2015-10-21-0/+236
| | | | | | | | | | | | System Management BIOS (SMBIOS) is a specification for how motherboard and system vendors present management information about their products in a standard format by extending the BIOS interface on Intel architecture systems. As of today the latest spec is 3.0 and can be downloaded from DMTF website. This commit adds a simple and minimum required implementation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move install_e820_map() out of zimage.cBin Meng2015-10-21-3/+3
| | | | | | | | install_e820_map() has nothing to do with zimage related codes. Move it to a dedicated place. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Allow disabling IGD on Intel QueensbayBin Meng2015-10-21-0/+5
| | | | | | | | | | Add a Kconfig option to disable the Integrated Graphics Device (IGD) so that it does not show in the PCI configuration space as a VGA disaplay controller. This gives a chance for U-Boot to run PCI/PCIe based graphics card's VGA BIOS and use that for the graphics console. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Configure MTRR to enable cacheBin Meng2015-09-16-0/+44
| | | | | | | | | | | | | | | | | Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs are accessed indirectly via the message port and not the traditional MSR mechanism. Only UC, WT and WB cache types are supported. We configure all the fixed range MTRRs with common values (VGA RAM as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as WB, which significantly improves the boot time performance. With this commit, it takes only 2 seconds for U-Boot to boot to shell on Intel Galileo board. Previously it took about 6 seconds. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: quark: Initialize thermal sensor properlyBin Meng2015-09-16-0/+14
| | | | | | | | | | | | | | Thermal sensor on Quark SoC needs to be properly initialized per Quark firmware writer guide, otherwise when booting Linux kernel, it triggers system shutdown because of wrong temperature in the thermal sensor is detected by the kernel driver (see below): [ 5.119819] thermal_sys: Critical temperature reached(206 C),shutting down [ 5.128997] Failed to start orderly shutdown: forcing the issue [ 5.135495] Emergency Sync complete Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Lock HMBOUND register before jumping to kernelBin Meng2015-09-16-0/+1
| | | | | | | | | | | | | | When Linux kernel boots, it hangs at: [ 0.829408] Intel Quark side-band driver registered This happens when Quark kernel Isolated Memory Region (IMR) driver tries to lock an IMR register to protect kernel's text and rodata sections. However in order to have IMR function correctly, HMBOUND register must be locked otherwise the system just hangs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Add clrbits, setbits, clrsetbits macros for message port accessBin Meng2015-09-16-0/+31
| | | | | | | | | On Intel Quark, lots of registers on the message port need be programmed. Add handy clrbits, setbits, clrsetbits macros for message port access. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: quark: Add PCIe/USB static register programming after memory initBin Meng2015-09-16-0/+22
| | | | | | | | | This adds static register programming for PCIe and USB after memory init as required by Quark firmware writer guide. Although not doing this did not cause any malfunction, just do it for safety. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Add USB PHY initialization supportBin Meng2015-09-09-0/+8
| | | | | | | | USB PHY needs to be properly initialized per Quark firmware writer guide, otherwise the EHCI controller on Quark SoC won't work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Enable PCIe controller on quark/galileoBin Meng2015-09-09-0/+42
| | | | | | | | | | | | | Quark SoC holds the PCIe controller in reset following a power on. U-Boot needs to release the PCIe controller from reset. The PCIe controller (D23:F0/F1) will not be visible in PCI configuration space and any access to its PCI configuration registers will cause system hang while it is held in reset. Enable PCIe controller per Quark firmware writer guide. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Optimize MRC execution timeBin Meng2015-09-09-0/+35
| | | | | | | | | | | | | | | | | Intel Quark SoC has a low end x86 processor with only 400MHz frequency. Currently it takes about 15 seconds for U-Boot to boot to shell and the most time consuming part is with MRC, which is about 12 seconds. MRC programs lots of registers on the SoC internal message bus indirectly accessed via pci bus. To speed up the boot, create an optimized version of pci config read/write dword routines which directly operate on PCI I/O ports. These two routines are inlined to provide better performance too. Now it only takes about 3 seconds to finish MRC, which is really fast (4 times faster than before). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Generate a valid ACPI tableSaket Sinha2015-08-26-0/+393
| | | | | | | | | | | | | | | | | Implement write_acpi_table() to create a minimal working ACPI table. This includes writing FACS, XSDT, RSDP, FADT, MCFG, MADT, DSDT & SSDT ACPI table entries. Use a Kconfig option GENERATE_ACPI_TABLE to tell U-Boot whether we need actually write the APCI table just like we did for PIRQ routing, MP table and SFI tables. With ACPI table existence, linux kernel gets control of power management, thermal management, configuration management and monitoring in hardware. Signed-off-by: Saket Sinha <saket.sinha89@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tidied up whitespace and aligned some tabs: Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: superio: Add keyboard controller support to smsc_lpc47m driverBin Meng2015-08-26-0/+3
| | | | | | | | | Add an api to enable and configure the integrated keyboard controller on SMSC LPC47m superio chipset. It also adds several macros to help future extension. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Remove calculate_relocation_address()Bin Meng2015-08-26-2/+0
| | | | | | | Now that we have generic routine to calculate relocation address, remove the x86 specific one which is now only used by coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coreboot: Increase memrange entry number to 32Bin Meng2015-08-26-6/+3
| | | | | | | | | Increase lib_sysinfo memrange entry number to 32 to sync with coreboot. This allows a complete E820 table to be reported to the kernel, as on some platforms (eg: Bayley Bay) having only 16 entires does not cover all the memory ranges. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop FSP error defines and use EFI insteadSimon Glass2015-08-14-11/+0
| | | | | | | | Now that we have an efi.h header we can use that for FSP error defines. Drop the FSP ones. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move the GDT into global_dataSimon Glass2015-08-14-1/+3
| | | | | | | | | Rather than keeping track of the Global Descriptor Table in its own memory we may as well put it in global_data with everything else. As a first step, stop using the separately allocated GDT. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Remove init_gd() functionSimon Glass2015-08-14-1/+0
| | | | | | | This is declared but no-longer exists. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow pirq_init() to return an errorSimon Glass2015-08-14-1/+3
| | | | | | | | This function can fail. In this case we should return the error rather than swallowing it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Split out fsp_init_phase_pci() code into a new functionSimon Glass2015-08-14-0/+7
| | | | | | | | | | | This code may be useful for boards that use driver model for PCI. Note: It would be better to have driver model automatically call this function somehow. However for now it is probably safer to have it under board control. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Do not assert VPD_IMAGE_REV when DEBUGBin Meng2015-08-14-2/+0
| | | | | | | | | | When using different release version of Intel FSP, the VPD_IMAGE_REV is different (ie: BayTrail Gold 3 is 0x0303 while Gold 4 is 0x0304). Remove the asserting of this so that U-Boot does not hang in a debug build. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add support for passing tables into U-BootSimon Glass2015-08-05-0/+1
| | | | | | | | | | | | The EFI stub provides information to U-Boot in a table. This includes the memory map which is needed to decide where to relocate U-Boot. Collect this information in the early init code and store it in global_data. Fix up the BIST code at the same time since we don't have it when booting from EFI and can assume it is 0. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* efi: Add 64-bit payload supportSimon Glass2015-08-05-1/+4
| | | | | | | | | | | | Most EFI implementations use 64-bit. Add a way to build U-Boot as a 64-bit EFI payload. The payload unpacks a (32-bit) U-Boot and starts it. This can be enabled for x86 boards at present. Signed-off-by: Simon Glass <sjg@chromium.org> Improvements to how the payload is built: Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a way to call 32-bit code from 64-bit modeSimon Glass2015-08-05-0/+9
| | | | | | | | | The procedure to drop from 64-bit mode to 32-bit is a bit messy. Add a function to take care of it. It requires identity-mapped pages and that the calling code is running below 4GB. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add an enum for some commonly-used GDT bitsSimon Glass2015-08-05-0/+18
| | | | | | | | Rather than add these as open-coded values, create an enum with the commonly used flags. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add support for U-Boot as an EFI applicationBen Stoltz2015-08-05-0/+10
| | | | | | | | | | Add the required x86 glue code. This includes the initial start-up, relocation and jumping to efi_main(). We also need to avoid fiddling with interrupts. Signed-off-by: Ben Stoltz <stoltz@google.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add asm/elf.h for x86-specific ELF definitionsSimon Glass2015-08-05-0/+46
| | | | | | | | Bring in this file from Linux 4.1. It supports relocation features specific to x86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* efi: Add start-up library codeSimon Glass2015-08-05-57/+2
| | | | | | | | | | | When running as an EFI application, U-Boot must request memory from EFI, and provide access to the boot services U-Boot needs. Add library code to perform these tasks. This includes efi_main() which is the entry point from EFI. U-Boot is built as a shared library. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow use of global_data with EFISimon Glass2015-08-05-0/+7
| | | | | | | | | | | | | | | On x86 the global_data pointer is provided through a somewhat-bizarre and x86-specific mechanism: the F segment register is set to a pointer to the start of global_data, so that accesses can use this build-in register. When running as an EFI application we don't want to mess with the Global Descriptor Table (GDT) and there is little advantage (in terms of code size) to doing so. Allow global_data to be a simple variable in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop unused copy_fdt_to_ram()Simon Glass2015-08-05-1/+0
| | | | | | | | This is now handled by generic U-Boot code so we do not need an x86 version. It is no-longer called, so remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Tidy up global_data flagsSimon Glass2015-08-05-4/+4
| | | | | | | | | | These flags now overlap some global ones. Adjust the x86-specific flags to avoid this. Since this requires a change to the start.S code, add a way for tools to find the 32-bit cold reset entry point. Previously this was at a fixed offset. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: baytrail: Update UPD setting for FSP Gold4 releaseBin Meng2015-08-05-1/+2
| | | | | | | | BayTrail FSP Gold4 release adds one UPD parameter to control IGD enable/disable. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Turn on PCIe ECAM address range decoding on Q35Bin Meng2015-07-28-0/+4
| | | | | | | Turn on PCIe ECAM address range decoding on Q35. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Enable I/O APIC chip select on PIIX3Bin Meng2015-07-28-1/+5
| | | | | | | | The PIIX3 chipset does not integrate an I/O APIC, instead it supports connecting to an external I/O APIC which needs to be enabled manually. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: mpspec: Allow platform to determine how PIRQ is connected to I/O APICBin Meng2015-07-28-0/+17
| | | | | | | | | Currently during writing MP table I/O interrupt assignment entry, we assume the PIRQ is directly mapped to I/O APIC INTPIN#16-23, which however is not always the case on some platforms. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: pci: Assign pci irqs to all functionsBin Meng2015-07-28-2/+1
| | | | | | | | We need walk through all functions within a PCI device and assign their IRQs accordingly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Change pci option rom area MTRR setting to cacheableBin Meng2015-07-28-0/+2
| | | | | | | Turn on cache on the pci option rom area to improve the performance. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Display correct CS/EIP/EFLAGS when there is an error codeBin Meng2015-07-28-3/+37
| | | | | | | | | Some exceptions cause an error code to be saved on the current stack after the EIP value. We should extract CS/EIP/EFLAGS from different position on the stack based on the exception number. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: delete unneeded declarations of disable_irq() and enable_irq()Masahiro Yamada2015-07-22-4/+0
| | | | | | | | | | | | | These two declarations in arch/x86/include/asm/interrupt.h conflict with ones in include/linux/compat.h, so x86 boards cannot include <linux/compat.h>. The comment /* arch/x86/lib/interrupts.c */ is bogus now, and we do not see any definitions of disable_irq() and enable_irq() in there. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Configure VESA parameters before loading Linux kernelBin Meng2015-07-14-0/+1
| | | | | | | | | Store VESA parameters to Linux setup header so that vesafb driver in the kernel could work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
* x86: Setup fixed range MTRRs for legacy regionsBin Meng2015-07-14-11/+16
| | | | | | | | | We should setup fixed range MTRRs for some legacy regions like VGA RAM and PCI ROM areas as uncacheable. Note FSP may setup these to other cache settings, but we can override this in x86_cpu_init_f(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Generate a valid MultiProcessor (MP) tableBin Meng2015-07-14-0/+10
| | | | | | | | | | | | | | | | | | | | Implement write_mp_table() to create a minimal working MP table. This includes an MP floating table, a configuration table header and all of the 5 base configuration table entries. The I/O interrupt assignment table entry is created based on the same information used in the creation of PIRQ routing table from device tree. A check duplicated entry logic is applied to prevent writing multiple I/O interrupt entries with the same information. Use a Kconfig option GENERATE_MP_TABLE to tell U-Boot whether we need actually write the MP table at the F seg, just like we did for PIRQ routing and SFI tables. With MP table existence, linux kernel will switch to I/O APIC and local APIC to process all the peripheral interrupts instead of 8259 PICs. This takes full advantage of the multicore hardware and the SMP kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add MultiProcessor (MP) table APIsBin Meng2015-07-14-0/+448
| | | | | | | | | | | The MP table provides a way for the operating system to support for symmetric multiprocessing as well as symmetric I/O interrupt handling with the local APIC and I/O APIC. We provide a bunch of APIs for U-Boot to write the floating table, configuration table header as well as base and extended table entries. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Remove inline for lapic access routinesBin Meng2015-07-14-124/+10
| | | | | | | | | Remove inline for lapic access routines and expose lapic_read() & lapic_write() as APIs to read/write lapic registers. Also move stop_this_cpu() to mp_init.c as it has nothing to do with lapic. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add I/O APIC register access routinesBin Meng2015-07-14-0/+24
| | | | | | | | | I/O APIC registers are addressed indirectly. Add io_apic_read() and io_apic_write() routines to help register access. Two macros for I/O APIC ID and version register offset are also added. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-15 03:45:48 +0000