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path: root/arch/x86/dts/link.dts
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* x86: Make chromebook_link the default board for corebootBin Meng2015-01-13-216/+0
* x86: ivybridge: Update microcode early in bootSimon Glass2015-01-13-3/+0
* x86: Clean up the board dts filesBin Meng2015-01-12-8/+3
* x86: Rename coreboot.dsti to serial.dtsiBin Meng2015-01-12-1/+1
* x86: ivybridge: Update the microcodeSimon Glass2014-12-18-2/+2
* x86: Move microcode updates into a separate directorySimon Glass2014-12-18-2/+2
* x86: dts: Add video information to the device treeSimon Glass2014-11-25-0/+13
* x86: dts: Add SATA settings for linkSimon Glass2014-11-25-0/+7
* x86: dts: Add LPC settings for linkSimon Glass2014-11-25-0/+8
* x86: dts: Move PCI peripherals into a pci nodeSimon Glass2014-11-25-13/+15
* x86: ivybridge: Implement SDRAM initSimon Glass2014-11-21-0/+111
* x86: chromebook_link: Enable GPIO supportSimon Glass2014-11-21-0/+3
* x86: dts: Add microcode updates for ivybridge CPUSimon Glass2014-11-21-0/+10
* x86: ivybridge: Add early LPC init so that serial worksSimon Glass2014-11-21-0/+1
* dm: x86: dts: Add additional info to the serial port nodeSimon Glass2014-10-23-1/+17
* x86: Add device tree information for Chrome OS ECSimon Glass2014-10-22-0/+18
* dts: move device tree sources to arch/$(ARCH)/dts/Masahiro Yamada2014-02-19-0/+35
generated by cgit v1.1 at 2024-08-25 09:04:34 +0000