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* x86: Add GDT descriptors for option ROMsSimon Glass2014-11-25-3/+6
| | | | | | | Option ROMs require a few additional descriptors. Add these, and remove the enum since we now have to access several descriptors from assembler. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add northbridge init functionsSimon Glass2014-11-25-0/+191
| | | | | | Add init for the northbridge, another part of the platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+521
| | | | | | Add the setup code for the CPU so that it can be used at full speed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add LAPIC setup codeSimon Glass2014-11-25-0/+58
| | | | | | | Add code to set up the Local Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop old CONFIG_INTEL_CORE_ARCH codeSimon Glass2014-11-25-28/+0
| | | | | | | This is no-longer used, so drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Refactor interrupt_init()Bin Meng2014-11-25-6/+20
| | | | | | | | | | | Rename interrupt_init() in arch/x86/lib/pcat_interrupts.c to i8259_init() and create a new interrupt_init() in arch/x86/cpu/interrupt.c to call i8259_init() followed by a call to cpu_init_interrupts(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Remove cpu_init_r() for x86Bin Meng2014-11-25-6/+0
| | | | | | | | | Since cpu_init_interrupts() was moved out of cpu_init_r(), it is useless to keep cpu_init_r() for x86, thus remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Call cpu_init_interrupts() from interrupt_init()Bin Meng2014-11-25-2/+0
| | | | | | | | | | | | | Currently cpu_init_interrupts() is called from cpu_init_r() to setup the interrupt and exception of the cpu core, but at that time the i8259 has not been initialized to mask all the irqs and remap the master i8259 interrupt vector base, so the whole system is at risk of being interrupted, and if interrupted, wrong interrupt/exception message is shown. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Add Intel speedstep and turbo mode codeSimon Glass2014-11-25-0/+99
| | | | | | | Intel chips have a turbo mode where they can run faster for a short period until they reach thermal limits. Add code to adjust and query this feature. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Set up XHCI USBSimon Glass2014-11-25-0/+33
| | | | | | Add init for XHCI so that high-speed USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Set up EHCI USBSimon Glass2014-11-25-0/+32
| | | | | | Add init for EHCI so that USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+246
| | | | | | Add code to set up the SATA interfaces on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add additional LPC initSimon Glass2014-11-25-1/+528
| | | | | | | Set up all the remaining pieces of the LPC (low-pin-count) peripheral in PCH (Peripheral Controller Hub). Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add PCH initSimon Glass2014-11-25-0/+124
| | | | | | Add required init for the Intel Platform Controller Hub in ivybridge. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-25-0/+140
| | | | | | Add basic setup for the PCH. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: pci: Add handlers before and after a PCI hose scanSimon Glass2014-11-25-0/+12
| | | | | | | | Some boards will want to do some setup before and after a PCI hose is scanned. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Factor out common values in the link scriptSimon Glass2014-11-25-7/+12
| | | | | | | | | Define the reset base in config.mk so that it does not need to be calculated twice in the link script. Also tidy up the START_16 and RESET_VEC_LOC values to fit with this new approach. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Ensure that all relocation data is included in the imageSimon Glass2014-11-25-1/+3
| | | | | | | | | Some toolchains put the relocation data into separate sections. Adjust the linker script to catch this case. Without relocation data, U-Boot will not boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Remove board_early_init_r()Simon Glass2014-11-25-11/+0
| | | | | | | | This function is not needed. Remove it to improve the generic init sequence slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add ivybridge directory to MakefileSimon Glass2014-11-25-0/+2
| | | | | | | It is now required to add subdirectories in the x86 cpu Makefile. Add this to fix a build breakage for chromebook_link. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-x86Tom Rini2014-11-24-125/+2595
|\ | | | | | | | | | | | | Conflicts: arch/x86/cpu/Makefile Signed-off-by: Tom Rini <trini@ti.com>
| * x86: ivybridge: Implement SDRAM initSimon Glass2014-11-21-5/+1037
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Add LAPIC supportSimon Glass2014-11-21-0/+3
| | | | | | | | | | | | | | | | The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Make show_boot_progress() commonSimon Glass2014-11-21-24/+24
| | | | | | | | | | | | | | This function can probably be used on all x86 boards, so move it into the common file. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Add early init for PCH devicesSimon Glass2014-11-21-0/+287
| | | | | | | | | | | | | | Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Perform Intel microcode update on bootSimon Glass2014-11-21-0/+157
| | | | | | | | | | | | | | Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Check BIST value on bootSimon Glass2014-11-21-0/+16
| | | | | | | | | | | | | | The built-in self test value should be checked before we continue booting. Refuse to continue if there is something wrong. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Perform initial CPU setupSimon Glass2014-11-21-0/+130
| | | | | | | | | | | | | | Set up the flex ratio (controls speed versus heat output) and a few other very early things. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Tidy up coreboot header usageSimon Glass2014-11-21-6/+6
| | | | | | | | | | | | | | | | There is no need to explicitly write 'arch-coreboot' when including headers, as when the arch directory points to coreboot the correct files will be used. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Add early LPC init so that serial worksSimon Glass2014-11-21-0/+61
| | | | | | | | | | | | | | | | The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: pci: Allow configuration before relocationSimon Glass2014-11-21-0/+50
| | | | | | | | | | | | | | | | | | | | Add simple PCI access routines for x86 which permit use before relocation. The normal PCI stack is still used, but for pre-relocation use there can only ever be a single hose. After relocation, fall back to the normal access, although even then on x86 machines there is normally only a single PCI bus. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Enable PCI in early initSimon Glass2014-11-21-0/+67
| | | | | | | | | | | | Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Support use of PCI before relocationSimon Glass2014-11-21-0/+21
| | | | | | | | | | | | | | | | Add support for using PCI before SDRAM is available, using early malloc() and global_data. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Refactor PCI to permit alternate initSimon Glass2014-11-21-15/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | We want access PCI earlier in the init sequence, so refactor the code so that it does not require use of a BSS variable to work. This will allow us to use early malloc() to store information about a PCI hose. Common PCI code moves to arch/x86/cpu/pci.c and a new board_pci_setup_hose() function is provided by boards to set up the (single) hose used by that board. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass2014-11-21-2/+162
| | | | | | | | | | | | | | | | Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Emit post codes in startup code for ChromebooksSimon Glass2014-11-21-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died. On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add chromebook_link boardSimon Glass2014-11-21-0/+263
| | | | | | | | | | | | | | | | | | | | | | | | This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directoryMasahiro Yamada2014-11-21-6/+6
| | | | | | | | | | | | | | | | | | | | The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile are redundant because the build system descends into the directory only when CONFIG_SYS_COREBOOT is defined. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Replace fill_processor_name() with cpu_get_name()Simon Glass2014-11-21-12/+15
| | | | | | | | | | | | | | | | This implementation has a 'cpu' prefix and returns a pointer to the string, avoiding the need for copying. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Fix a warning with gcc 4.4.4Simon Glass2014-11-21-0/+1
| | | | | | | | | | | | | | This warning appears even though it seems that the compiler could work it out. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Do CPU identification in the early phaseBin Meng2014-11-21-43/+229
| | | | | | | | | | | | | | The CPU identification happens in x86_cpu_init_f() and corresponding fields are saved in the global data for later use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Save the BIST value on resetSimon Glass2014-11-21-4/+12
| | | | | | | | | | | | | | | | | | | | The built in self test value is available in register eax on start-up. Save it so that it can be accessed later. Unfortunately we must wait until the global_data is available before we can do this, so there is a little bit of shuffling to keep it around. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Fix up some missing prototypesSimon Glass2014-11-21-8/+5
| | | | | | | | | | | | | | Some functions are missing prototypes. Fix those that are specific to x86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Use the standard arch_cpu_init() functionSimon Glass2014-11-21-7/+5
| | | | | | | | | | | | | | | | Instead of an x86-specific cpu_init_f() function, use the normal U-Boot one for this purpose. Also remove a useless/misleading comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Use the standard dram_init() functionSimon Glass2014-11-21-7/+4
| | | | | | | | | | | | | | | | Instead of having an x86-specific DRAM init function, adjust things so we can use the normal one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Tidy up global descriptor table setupSimon Glass2014-11-21-3/+16
| | | | | | | | | | | | | | | | This code is a little muddled, so tidy it up. Make sure that we put the GDT in the right place and set it up properly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Invalidate TLB as early as possibleSimon Glass2014-11-21-0/+3
| | | | | | | | | | | | | | | | We should invalidate the TLB right at the start to ensure that we don't get false address translations even though paging is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Remove board_init16() call which is not usedSimon Glass2014-11-21-9/+1
| | | | | | | | | | | | | | | | This allows a board to do very early init, but no boards need to do this. We may as well drop this feature. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directoryMasahiro Yamada2014-11-23-7/+7
| | | | | | | | | | | | | | | | | | | | The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile are redundant because the build system descends into the directory only when CONFIG_SYS_COREBOOT is defined. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | kbuild: Descend into SOC directory from CPU directoryMasahiro Yamada2014-11-23-0/+2
| | | | | | | | | | | | | | | | | | Some CPUs of some architectures have SOC directories. At present, the build system directly descends into SOC directories from the top Makefile, but it should generally descend into each directory from its parent directory. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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