summaryrefslogtreecommitdiff
path: root/arch/x86/cpu
Commit message (Expand)AuthorAgeLines
* x86: Add GDT descriptors for option ROMsSimon Glass2014-11-25-3/+6
* x86: ivybridge: Add northbridge init functionsSimon Glass2014-11-25-0/+191
* x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+521
* x86: Add LAPIC setup codeSimon Glass2014-11-25-0/+58
* x86: Drop old CONFIG_INTEL_CORE_ARCH codeSimon Glass2014-11-25-28/+0
* x86: Refactor interrupt_init()Bin Meng2014-11-25-6/+20
* x86: Remove cpu_init_r() for x86Bin Meng2014-11-25-6/+0
* x86: Call cpu_init_interrupts() from interrupt_init()Bin Meng2014-11-25-2/+0
* x86: Add Intel speedstep and turbo mode codeSimon Glass2014-11-25-0/+99
* x86: ivybridge: Set up XHCI USBSimon Glass2014-11-25-0/+33
* x86: ivybridge: Set up EHCI USBSimon Glass2014-11-25-0/+32
* x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+246
* x86: ivybridge: Add additional LPC initSimon Glass2014-11-25-1/+528
* x86: ivybridge: Add PCH initSimon Glass2014-11-25-0/+124
* x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-25-0/+140
* x86: pci: Add handlers before and after a PCI hose scanSimon Glass2014-11-25-0/+12
* x86: Factor out common values in the link scriptSimon Glass2014-11-25-7/+12
* x86: Ensure that all relocation data is included in the imageSimon Glass2014-11-25-1/+3
* x86: Remove board_early_init_r()Simon Glass2014-11-25-11/+0
* x86: Add ivybridge directory to MakefileSimon Glass2014-11-25-0/+2
* Merge git://git.denx.de/u-boot-x86Tom Rini2014-11-24-125/+2595
|\
| * x86: ivybridge: Implement SDRAM initSimon Glass2014-11-21-5/+1037
| * x86: ivybridge: Add LAPIC supportSimon Glass2014-11-21-0/+3
| * x86: Make show_boot_progress() commonSimon Glass2014-11-21-24/+24
| * x86: ivybridge: Add early init for PCH devicesSimon Glass2014-11-21-0/+287
| * x86: ivybridge: Perform Intel microcode update on bootSimon Glass2014-11-21-0/+157
| * x86: ivybridge: Check BIST value on bootSimon Glass2014-11-21-0/+16
| * x86: ivybridge: Perform initial CPU setupSimon Glass2014-11-21-0/+130
| * x86: Tidy up coreboot header usageSimon Glass2014-11-21-6/+6
| * x86: ivybridge: Add early LPC init so that serial worksSimon Glass2014-11-21-0/+61
| * x86: pci: Allow configuration before relocationSimon Glass2014-11-21-0/+50
| * x86: ivybridge: Enable PCI in early initSimon Glass2014-11-21-0/+67
| * x86: Support use of PCI before relocationSimon Glass2014-11-21-0/+21
| * x86: Refactor PCI to permit alternate initSimon Glass2014-11-21-15/+35
| * x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass2014-11-21-2/+162
| * x86: Emit post codes in startup code for ChromebooksSimon Glass2014-11-21-1/+6
| * x86: Add chromebook_link boardSimon Glass2014-11-21-0/+263
| * x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directoryMasahiro Yamada2014-11-21-6/+6
| * x86: Replace fill_processor_name() with cpu_get_name()Simon Glass2014-11-21-12/+15
| * x86: Fix a warning with gcc 4.4.4Simon Glass2014-11-21-0/+1
| * x86: Do CPU identification in the early phaseBin Meng2014-11-21-43/+229
| * x86: Save the BIST value on resetSimon Glass2014-11-21-4/+12
| * x86: Fix up some missing prototypesSimon Glass2014-11-21-8/+5
| * x86: Use the standard arch_cpu_init() functionSimon Glass2014-11-21-7/+5
| * x86: Use the standard dram_init() functionSimon Glass2014-11-21-7/+4
| * x86: Tidy up global descriptor table setupSimon Glass2014-11-21-3/+16
| * x86: Invalidate TLB as early as possibleSimon Glass2014-11-21-0/+3
| * x86: Remove board_init16() call which is not usedSimon Glass2014-11-21-9/+1
* | x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directoryMasahiro Yamada2014-11-23-7/+7
* | kbuild: Descend into SOC directory from CPU directoryMasahiro Yamada2014-11-23-0/+2
generated by cgit v1.1 at 2024-12-28 13:41:39 +0000