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* x86: Remove HAVE_ACPI_RESUMEBin Meng2015-12-09-34/+0
* x86: Remove CPU_INTEL_SOCKET_RPGA989Bin Meng2015-12-09-11/+4
* x86: Clean up ivybridge/chrome Kconfig optionsBin Meng2015-12-09-30/+0
* x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGEBin Meng2015-12-09-33/+1
* x86: Move i8254_init() to x86_cpu_init_f()Bin Meng2015-12-09-0/+5
* x86: tsc: Remove legacy timer codesBin Meng2015-12-01-6/+0
* x86: Convert to use driver model timerBin Meng2015-12-01-39/+0
* x86: Remove MIN_PORT80_KCLOCKS_DELAYBin Meng2015-12-01-18/+0
* x86: Remove legacy pci codesBin Meng2015-11-13-45/+0
* x86: qemu: Convert to use driver model pciBin Meng2015-11-13-50/+0
* x86: qemu: Move chipset-specific codes from pci.c to qemu.cBin Meng2015-11-13-72/+82
* x86: qemu: Remove call to vgabios executionBin Meng2015-11-13-18/+1
* x86: queensbay: Really disable IGDBin Meng2015-11-13-6/+20
* x86: Rename pcat_ to i8254 and i8259 accordinglyBin Meng2015-11-13-1/+1
* x86: ivybridge: Enable the MRC cacheBin Meng2015-10-21-8/+2
* x86: ivybridge: Measure the MRC code execution timeSimon Glass2015-10-21-0/+3
* x86: ivybridge: Fix car_uninit() to correctly set run stateSimon Glass2015-10-21-1/+1
* x86: ivybridge: Check the RTC return valueSimon Glass2015-10-21-3/+10
* x86: ivybridge: Use 'ret' instead of 'rcode'Simon Glass2015-10-21-8/+8
* x86: chromebook_link: Enable the debug UARTSimon Glass2015-10-21-0/+7
* x86: Init the debug UART if enabledSimon Glass2015-10-21-8/+3
* x86: Pass correct cpu_index to ap_init()Bin Meng2015-10-21-2/+2
* x86: quark: Implement mrc cacheBin Meng2015-10-21-7/+64
* x86: ivybridge: Correct two typos for MRCBin Meng2015-10-21-2/+2
* x86: baytrail: Issue full system reset in reset_cpu()Bin Meng2015-10-21-0/+6
* x86: baytrail: Save mrc cache to spi flashBin Meng2015-10-21-0/+19
* x86: Use struct mrc_region to describe a mrc regionBin Meng2015-10-21-1/+1
* x86: ivybridge: Use APIs provided in the mrccache libBin Meng2015-10-21-108/+4
* x86: Move mrccache.[c|h] to a common placeBin Meng2015-10-21-159/+1
* x86: Initialize GDT entry 1 to be the 32-bit CS as wellBin Meng2015-10-21-1/+6
* x86: Allow disabling IGD on Intel QueensbayBin Meng2015-10-21-0/+27
* x86: ivybridge: Remove the dead codes that programs pci bridgeBin Meng2015-10-21-32/+0
* x86: quark: Configure MTRR to enable cacheBin Meng2015-09-16-0/+67
* x86: quark: Initialize thermal sensor properlyBin Meng2015-09-16-0/+40
* x86: quark: Lock HMBOUND register before jumping to kernelBin Meng2015-09-16-0/+3
* x86: quark: Convert to use clrbits, setbits, clrsetbits macrosBin Meng2015-09-16-51/+21
* x86: quark: Add PCIe/USB static register programming after memory initBin Meng2015-09-16-0/+64
* x86: Convert to use driver model eth on quark/galileoBin Meng2015-09-16-19/+0
* x86: quark: Add USB PHY initialization supportBin Meng2015-09-09-0/+41
* x86: Convert to use driver model pci on quark/galileoBin Meng2015-09-09-76/+0
* x86: Enable PCIe controller on quark/galileoBin Meng2015-09-09-0/+63
* x86: quark: Avoid chicken and egg problemBin Meng2015-09-09-15/+15
* x86: quark: Optimize MRC execution timeBin Meng2015-09-09-22/+22
* x86: coreboot: Convert to use more dm driversBin Meng2015-09-09-6/+0
* x86: Add DSDT table for supporting ACPI on QEMUSaket Sinha2015-08-26-1/+712
* x86: Add ACPI table support to QEMUSaket Sinha2015-08-26-0/+177
* x86: baytrail: Remove the fsp_init_phase_pci() callBin Meng2015-08-26-7/+1
* x86: queensbay: Move unprotect_spi_flash() to arch_misc_init()Bin Meng2015-08-26-2/+2
* x86: fsp: Add comments about U-Boot entering start.S twiceBin Meng2015-08-26-2/+4
* x86: fsp: Enlarge the size of malloc() pool before relocationBin Meng2015-08-26-0/+8
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