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* x86: broadwell: Correct I/O APIC IDBin Meng2016-05-23-1/+2
* x86: quark: Assign a unique I/O APIC IDBin Meng2016-05-23-0/+4
* x86: Call lapic_setup() in interrupt_init()Bin Meng2016-05-23-7/+5
* x86: Remove SMP limitation in lapic_setup()Bin Meng2016-05-23-6/+1
* x86: Don't touch IA32_APIC_BASE MSR on Intel QuarkBin Meng2016-05-23-12/+16
* x86: Reserve configuration tables in high memoryBin Meng2016-05-23-3/+8
* x86: Unify reserve_arch() for all x86 boardsBin Meng2016-05-23-27/+12
* x86: Fix up PIRQ routing table checksum earlierBin Meng2016-05-23-0/+4
* x86: Call board_final_cleanup() in last_stage_init()Bin Meng2016-05-23-9/+21
* x86: qemu: rename qemu/acpi_table.cMiao Yan2016-05-23-2/+1
* cmd: qfw: bring ACPI generation code into qfw coreMiao Yan2016-05-23-209/+0
* cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]Miao Yan2016-05-23-4/+4
* x86: qemu: add comment about qfw register endiannessMiao Yan2016-05-23-1/+8
* x86: qemu: move x86 specific operations out of qfw coreMiao Yan2016-05-23-1/+38
* x86: qemu: split qfw command interface and qfw coreMiao Yan2016-05-23-3/+6
* cmd: qfw: remove qemu_fwcfg_free_files()Miao Yan2016-05-23-2/+11
* x86: qemu: fix ACPI Kconfig optionsMiao Yan2016-05-23-1/+1
* x86: qemu: Move qfw command over to cmd and add Kconfig entryTom Rini2016-05-23-574/+248
* x86: baytrail: Generate ACPI FADT/MADT tablesBin Meng2016-05-23-0/+164
* x86: irq: Enable SCI on IRQ9Bin Meng2016-05-23-0/+22
* x86: irq: Reserve IRQ9 for ACPI in PIC modeBin Meng2016-05-23-0/+5
* x86: Drop asm/acpi.hBin Meng2016-05-23-3/+0
* dm: Rename disk uclass to ahciSimon Glass2016-05-17-4/+4
* x86: Correct typo of Miao Yan's email addressBin Meng2016-04-22-1/+1
* x86: qemu: Drop our own ACPI implementationBin Meng2016-04-22-890/+0
* arm: x86: Drop command-line code when CONFIG_CMDLINE is disabledSimon Glass2016-03-22-0/+4
* x86: Support a chained-boot development flowSimon Glass2016-03-17-0/+80
* x86: ivybridge: Convert to use the common SDRAM codeSimon Glass2016-03-17-311/+83
* x86: Add common SDRAM-init codeSimon Glass2016-03-17-0/+272
* x86: Move common PCH code into a common placeSimon Glass2016-03-17-31/+43
* x86: Add a function to set the IOAPIC IDSimon Glass2016-03-17-0/+16
* x86: broadwell: Add support for high-speed I/O lane with MESimon Glass2016-03-17-0/+58
* x86: broadwell: Add support for SDRAM setupSimon Glass2016-03-17-0/+308
* x86: broadwell: Add power-control supportSimon Glass2016-03-17-0/+91
* x86: broadwell: Add reference code supportSimon Glass2016-03-17-0/+114
* x86: broadwell: Add an LPC driverSimon Glass2016-03-17-0/+78
* x86: broadwell: Add a northbridge driverSimon Glass2016-03-17-0/+60
* x86: broadwell: Add a SATA driverSimon Glass2016-03-17-0/+270
* x86: broadwell: Add a pinctrl driverSimon Glass2016-03-17-0/+279
* x86: broadwell: Add a PCH driverSimon Glass2016-03-17-0/+686
* x86: Add basic support for broadwellSimon Glass2016-03-17-0/+799
* x86: Update microcode for secondary CPUsSimon Glass2016-03-17-2/+7
* x86: ivybridge: Show microcode version for each coreSimon Glass2016-03-17-1/+2
* x86: Record the CPU details when starting each coreSimon Glass2016-03-17-1/+11
* x86: Move common MRC Kconfig options to the common fileSimon Glass2016-03-17-26/+1
* x86: Move Intel Management Engine code to a common placeSimon Glass2016-03-17-35/+25
* x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass2016-03-17-4/+4
* x86: Move common CPU code to its own placeSimon Glass2016-03-17-74/+118
* x86: Move common LPC code to its own placeSimon Glass2016-03-17-83/+107
* x86: Add the root-complex block to common intel registersSimon Glass2016-03-17-2/+5
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