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* x86: coreboot: Configure pci memory regionsBin Meng2015-01-13-2/+28
* x86: coreboot: Move coreboot-specific defines from coreboot.h to KconfigBin Meng2015-01-13-0/+15
* x86: coreboot: Set up timer base correctlyBin Meng2015-01-13-13/+20
* x86: fsp: Drop get_hob_type() and get_hob_length()Bin Meng2015-01-13-7/+7
* x86: ivybridge: Update microcode early in bootSimon Glass2015-01-13-10/+34
* x86: Disable CAR before relocation on platforms that need itSimon Glass2015-01-13-0/+8
* x86: ivybridge: Add a way to turn off the CARSimon Glass2015-01-13-0/+46
* x86: ivybridge: Request MTRRs for DRAM regionsSimon Glass2015-01-13-0/+10
* x86: ivybridge: Set up an MTRR for the video frame bufferSimon Glass2015-01-13-0/+7
* x86: Add support for MTRRsSimon Glass2015-01-13-18/+98
* x86: ivybridge: Drop support for ROM cachingSimon Glass2015-01-13-25/+0
* x86: ivybridge: Only run the Video BIOS when video is enabledSimon Glass2015-01-13-1/+8
* x86: Simplify the fsp hob access functionsBin Meng2015-01-12-62/+72
* pci: Make pci apis usable before relocationBin Meng2015-01-12-4/+4
* x86: Support pci bus scan in the early phaseBin Meng2015-01-12-0/+1
* x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.cBin Meng2015-01-12-0/+2
* x86: Clean up the FSP support codesBin Meng2014-12-18-144/+129
* x86: crownbay: Add SDHCI supportBin Meng2014-12-18-1/+48
* x86: crownbay: Add SPI flash supportBin Meng2014-12-18-1/+25
* x86: Use consistent name XXX_ADDR for binary blob flash addressBin Meng2014-12-18-5/+5
* x86: Add queensbay and crownbay Kconfig filesBin Meng2014-12-18-0/+79
* x86: Enable the queensbay cpu directory buildBin Meng2014-12-18-0/+1
* x86: Convert microcode format to device-tree-onlySimon Glass2014-12-18-7/+4
* x86: Add basic support to queensbay platform and crownbay boardBin Meng2014-12-18-0/+323
* x86: Correct problems in the microcode loadingSimon Glass2014-12-18-10/+15
* x86: ivybridge: Update the microcodeSimon Glass2014-12-18-0/+2
* x86: Support Intel FSP initialization path in start.SBin Meng2014-12-13-0/+14
* x86: Add post failure codes for bist and carBin Meng2014-12-13-0/+1
* x86: queensbay: Adapt FSP support codesBin Meng2014-12-13-17/+27
* x86: Initial import from Intel FSP release for Queensbay platformBin Meng2014-12-13-0/+426
* x86: Clean up asm-offsetsBin Meng2014-12-13-1/+2
* Replace <compiler.h> with <linux/compiler.h>Masahiro Yamada2014-12-08-1/+2
* x86: Add initial video device init for Intel GMASimon Glass2014-11-25-1/+925
* x86: Add GDT descriptors for option ROMsSimon Glass2014-11-25-3/+6
* x86: ivybridge: Add northbridge init functionsSimon Glass2014-11-25-0/+191
* x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+521
* x86: Add LAPIC setup codeSimon Glass2014-11-25-0/+58
* x86: Drop old CONFIG_INTEL_CORE_ARCH codeSimon Glass2014-11-25-28/+0
* x86: Refactor interrupt_init()Bin Meng2014-11-25-6/+20
* x86: Remove cpu_init_r() for x86Bin Meng2014-11-25-6/+0
* x86: Call cpu_init_interrupts() from interrupt_init()Bin Meng2014-11-25-2/+0
* x86: Add Intel speedstep and turbo mode codeSimon Glass2014-11-25-0/+99
* x86: ivybridge: Set up XHCI USBSimon Glass2014-11-25-0/+33
* x86: ivybridge: Set up EHCI USBSimon Glass2014-11-25-0/+32
* x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+246
* x86: ivybridge: Add additional LPC initSimon Glass2014-11-25-1/+528
* x86: ivybridge: Add PCH initSimon Glass2014-11-25-0/+124
* x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-25-0/+140
* x86: pci: Add handlers before and after a PCI hose scanSimon Glass2014-11-25-0/+12
* x86: Factor out common values in the link scriptSimon Glass2014-11-25-7/+12
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