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* x86: tnc: Remove IGD and SDVO devices from driver modelBin Meng2016-02-05-0/+36
| | | | | | | | | | | | | | | | | | | With recent DM PCI changes to vesa_fb driver, external graphics card does not work any more. This is because: after setting the function disable bit, IGD and SDVO devices will disappear in the PCI configuration space. This however creates an inconsistent state from a driver model PCI controller point of view, as these two PCI devices are still attached to its parent's child device list as maintained by the driver model. Some driver model PCI APIs like dm_pci_find_class() used in the vesa_fb driver, are referring to the list to speed up the finding process instead of re-enumerating the whole PCI bus, so it gets the stale cached data which is wrong. To fix this, manually remove these two devices. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: tnc: Use DM PCI API in disable_igd()Bin Meng2016-02-05-3/+19
| | | | | | | | | Once we get udevice of IGD and SDVO, we can use its udevice to access PCI configuration space with dm_pci_write_config32(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: tnc: Change disable_igd() to have a return valueBin Meng2016-02-05-3/+7
| | | | | | | | | So far disable_igd() does not have any return value, but we may need that in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: irq: Convert to use DM PCI APIBin Meng2016-02-05-1/+1
| | | | | | | | | Now that we have irq router's udevice passed as a parameter, it's time to start using the DM PCI API instead of those legacy ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: tnc: Drop unprotect_spi_flash()Bin Meng2016-02-05-16/+0
| | | | | | | | | Unprotecting SPI flash is now handled in the SPI controller driver, via a call to the PCH driver. Drop the ad-hoc version. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* dm: x86: queensbay: Add an interrupt driverSimon Glass2016-01-24-38/+66
| | | | | | | | | Add a driver for interrupts on queensbay and move the code currently in cpu_irq_init() into its probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: Set up interrupt routing from interrupt_init()Simon Glass2016-01-24-1/+1
| | | | | | | | | | | | | | | At present interrupt routing is set up from arch_misc_init(). We can do it a little later instead, in interrupt_init(). This removes the manual pirq_init() call. Where the platform does not have an interrupt router defined in its device tree, no error is generated. Some platforms do not have this. Drop pirq_init() since it is no-longer used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-01-14-7/+7
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| * x86: fsp: Set up init runtime buffer in update_fsp_configs()Bin Meng2016-01-13-1/+7
| | | | | | | | | | | | | | | | | | fsp_init() runtime buffer parameter might be different across different platforms. Move this to update_fsp_configs(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * x86: queensbay: Remove invalid comments in update_fsp_configs()Bin Meng2016-01-13-6/+0
| | | | | | | | | | | | | | | | Those comments in update_fsp_configs() are not correct. Remove them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Rename update_fsp_upd() and change its signatureBin Meng2016-01-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | To support platform-specific configurations (might not always be UPD on some platform), use a better name update_fsp_configs() and accepct struct fsp_config_data as its parameter so that platform codes can handle whatever configuration data for that FSP. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | dm: Convert PCI MMC over to use DM PCI APISimon Glass2016-01-12-2/+2
|/ | | | | | | | | | | | | | At present pci_mmc_init() does not correctly use the PCI function since the list it passes is not terminated. The array size passed to pci_mmc_init() is actually not used correctly. Fix this and adjust the pci_mmc_init() to scan all available MMC devices. Adjust this code to use the new driver model PCI API. This should move over to the new MMC uclass at some point. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Convert to use driver model timerBin Meng2015-12-01-3/+0
| | | | | | | Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Really disable IGDBin Meng2015-11-13-6/+20
| | | | | | | | | | | | | | | | | | | | | | According to Atom E6xx datasheet, setting VGA Disable (bit17) of Graphics Controller register (offset 0x50) prevents IGD (D2:F0) from reporting itself as a VGA display controller class in the PCI configuration space, and should also prevent it from responding to VGA legacy memory range and I/O addresses. However test result shows that with just VGA Disable bit set and a PCIe graphics card connected to one of the PCIe controllers on the E6xx, accessing the VGA legacy space still causes system hang. After a number of attempts, it turns out besides VGA Disable bit, the SDVO (D3:F0) device should be disabled to make it work. To simplify, use the Function Disable register (offset 0xc4) to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these two devices will be completely disabled (invisible in the PCI configuration space) unless a system reset is performed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Allow disabling IGD on Intel QueensbayBin Meng2015-10-21-0/+27
| | | | | | | | | | Add a Kconfig option to disable the Integrated Graphics Device (IGD) so that it does not show in the PCI configuration space as a VGA disaplay controller. This gives a chance for U-Boot to run PCI/PCIe based graphics card's VGA BIOS and use that for the graphics console. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Move unprotect_spi_flash() to arch_misc_init()Bin Meng2015-08-26-2/+2
| | | | | | | | | | With dm pci conversion, pci config read/write in unprotect_spi_flash() silently fails as at that time dm pci is not ready and bus enumeration is not done yet. Actually we don't need to do this in that early phase, hence we delay this call to arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Allow pirq_init() to return an errorSimon Glass2015-08-14-3/+1
| | | | | | | | This function can fail. In this case we should return the error rather than swallowing it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Convert to use driver model pci on queensbay/crownbayBin Meng2015-07-28-52/+0
| | | | | | Move to driver model pci for Intel queensbay/crownbay. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: queensbay: Change CPU_ADDR_BITS to 32Bin Meng2015-07-14-0/+4
| | | | | | | | | Per CPUID:80000008h result, the maximum physical address bits of TunnelCreek processor is 32 instead of default 36. This will fix the incorrect decoding of MTRR range mask. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Change PCIe root ports' interrupt routingBin Meng2015-07-14-6/+7
| | | | | | | | | | | | | | | So far interrupt routing works pretty well for any on-chip devices on Intel Crown Bay. When inserting any PCIe card to any PCIe slot, Linux kernel is smart enough to do interrupt swizzling and figure out device's irq using its parent bridge's interrupt routing info all the way up to its root port. In U-Boot all PCIe root ports' interrupts were routed to PIRQ E/F/G/H before, while actually all PCIe downstream ports received INTx are routed to PIRQ A/B/C/D directly and not configurable. Now we change this mapping so that any external PCIe device can work correctly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Refactor PIRQ routing supportBin Meng2015-06-04-244/+39
| | | | | | | | | | | | PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Implement PIRQ routingBin Meng2015-04-29-2/+252
| | | | | | | | Implement Intel Queensbay platform-specific PIRQ routing support. The chipset PIRQ routing setup is called in the arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Avoid using PCH prefixBin Meng2015-04-29-2/+2
| | | | | | | | | | The prefix PCH was taken from ivybridge port. However Queensbay platform official document does not mention PCH. It is composed of TunnelCreek processor and Topcliff IOH chipset. For accuracy, avoid using PCH prefix in the macro. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add a x86_ prefix to the x86-specific PCI functionsSimon Glass2015-04-16-2/+2
| | | | | | | | | | | | These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow FSP Kconfig settings for all x86Simon Glass2015-02-06-38/+0
| | | | | | | | While queensbay is the first chip with these settings, others will want to use them too. Make them common. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: mmc: Move common FSP functions into a common fileSimon Glass2015-02-06-72/+3
| | | | | | | | | | | | Since these board functions seem to be the same for all boards which use FSP, move them into a common file. We can adjust this later if future FSPs need more flexibility. This creates a generic PCI MMC device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Make CAR and DRAM FSP code commonSimon Glass2015-02-05-206/+1
| | | | | | | | | For now this code seems to be the same for all FSP platforms. Make it common until we see what differences are required. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common FSP code into a common locationSimon Glass2015-02-05-413/+5
| | | | | | Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Drop get_hob_type() and get_hob_length()Bin Meng2015-01-13-7/+7
| | | | | | | | | | | These two are not worth having separate inline functions as they are really simple, so drop them. Also changed 'type' parameter of fsp_get_next_hob() from u16 to uint. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Simplify the fsp hob access functionsBin Meng2015-01-12-62/+72
| | | | | | | | | Remove the troublesome union hob_pointers so that some annoying casts are no longer needed in those hob access routines. This also improves the readability. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Clean up the FSP support codesBin Meng2014-12-18-144/+129
| | | | | | | | | | | | | | | | | | | | | | | | | This is the follow-on patch to clean up the FSP support codes: - Remove the _t suffix on the structures defines - Use __packed for structure defines - Use U-Boot's assert() - Use standard bool true/false - Remove read_unaligned64() - Use memcmp() in the compare_guid() - Remove the cast in the memset() call - Replace some magic numbers with macros - Use panic() when no valid FSP image header is found - Change some FSP utility routines to use an fsp_ prefix - Add comment blocks for asm_continuation and fsp_init_done - Remove some casts in find_fsp_header() - Change HOB access macros to static inline routines - Add comments to mention find_fsp_header() may be called in a stackless environment - Add comments to mention init(&params) in fsp_init() cannot be removed Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Add SDHCI supportBin Meng2014-12-18-1/+48
| | | | | | | | | There are two standard SD card slots on the Crown Bay board, which are connected to the Topcliff PCH SDIO controllers. Enable the SDHC support so that we can use them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Add SPI flash supportBin Meng2014-12-18-1/+25
| | | | | | | | | The Crown Bay board has an SST25VF016B flash connected to the Tunnel Creek processor SPI controller used as the BIOS media where U-Boot is stored. Enable this flash support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Use consistent name XXX_ADDR for binary blob flash addressBin Meng2014-12-18-4/+4
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add queensbay and crownbay Kconfig filesBin Meng2014-12-18-0/+79
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Convert microcode format to device-tree-onlySimon Glass2014-12-18-7/+4
| | | | | | | | | | To avoid having two microcode formats, adjust the build system to support obtaining the microcode from the device tree, even in the case where it must be made available before the device tree can be accessed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add basic support to queensbay platform and crownbay boardBin Meng2014-12-18-0/+323
| | | | | | | | | | | Implement minimum required functions for the basic support to queensbay platform and crownbay board. Currently the implementation is to call fsp_init() in the car_init(). We may move that call to cpu_init_f() in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Adapt FSP support codesBin Meng2014-12-13-17/+27
| | | | | | | Use inline assembly codes to call FspNotify() to make sure parameters are passed on the stack as required by the FSP calling convention. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Initial import from Intel FSP release for Queensbay platformBin Meng2014-12-13-0/+426
This is the initial import from Intel FSP release for Queensbay platform (Tunnel Creek processor and Topcliff Platform Controller Hub), which can be downloaded from Intel website. For more details, check http://www.intel.com/fsp. Note: U-Boot coding convention was applied to these codes, so it looks completely different from the original Intel release. Also update FSP support codes license header to use SPDX ID. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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