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| author | Bin Meng <bmeng.cn@gmail.com> | 2014-12-17 15:50:44 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2014-12-18 17:26:07 -0700 |
| commit | adfe3b247a7a281931f0fd865e9d00600e9dd384 (patch) | |
| tree | e2a388dc0df283233d937f35433ab416b3d48307 /arch/x86/cpu/queensbay | |
| parent | 63faf2507d263bbd6285b3fe637fd80df05a58a0 (diff) | |
| download | u-boot-imx-adfe3b247a7a281931f0fd865e9d00600e9dd384.zip u-boot-imx-adfe3b247a7a281931f0fd865e9d00600e9dd384.tar.gz u-boot-imx-adfe3b247a7a281931f0fd865e9d00600e9dd384.tar.bz2 | |
x86: crownbay: Add SPI flash support
The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/queensbay')
| -rw-r--r-- | arch/x86/cpu/queensbay/tnc.c | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 8b9815f..8637cdc 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -6,18 +6,42 @@ #include <common.h> #include <asm/io.h> +#include <asm/pci.h> #include <asm/post.h> +#include <asm/arch/tnc.h> #include <asm/arch/fsp/fsp_support.h> #include <asm/processor.h> +static void unprotect_spi_flash(void) +{ + u32 bc; + + bc = pci_read_config32(PCH_LPC_DEV, 0xd8); + bc |= 0x1; /* unprotect the flash */ + pci_write_config32(PCH_LPC_DEV, 0xd8, bc); +} + int arch_cpu_init(void) { + struct pci_controller *hose; + int ret; + post_code(POST_CPU_INIT); #ifdef CONFIG_SYS_X86_TSC_TIMER timer_set_base(rdtsc()); #endif - return x86_cpu_init_f(); + ret = x86_cpu_init_f(); + if (ret) + return ret; + + ret = pci_early_init_hose(&hose); + if (ret) + return ret; + + unprotect_spi_flash(); + + return 0; } int print_cpuinfo(void) |