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path: root/arch/x86/cpu/ivybridge/cpu.c
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* x86: Move common PCH code into a common placeSimon Glass2016-03-17-0/+1
* x86: Move common CPU code to its own placeSimon Glass2016-03-17-74/+6
* x86: Create a common header for Intel register accessSimon Glass2016-03-17-0/+1
* x86: Move microcode code to a common locationSimon Glass2016-03-17-1/+1
* dm: Use uclass_first_device_err() where it is usefulSimon Glass2016-03-14-9/+5
* x86: ivybridge: Convert enable_usb_bar() to use DM PCI APISimon Glass2016-01-24-17/+17
* x86: ivybridge: Use the I2C driver to perform SMbus initSimon Glass2016-01-24-36/+3
* x86: ivybridge: Do the SATA init before relocationSimon Glass2016-01-24-0/+3
* x86: ivybridge: Move GPIO init to the LPC init() methodSimon Glass2016-01-24-4/+0
* x86: ivybridge: Move graphics init much laterSimon Glass2016-01-24-1/+0
* x86: ivybridge: Probe the LPC in CPU initSimon Glass2016-01-24-3/+2
* x86: ivybridge: Move northbridge init into the probe() methodSimon Glass2016-01-24-0/+2
* x86: ivybridge: Rename bd82x6x_init()Simon Glass2016-01-24-0/+8
* x86: ivybridge: Move more init to the probe() functionSimon Glass2016-01-24-43/+0
* x86: ivybridge: Move lpc_early_init() to probe()Simon Glass2016-01-24-9/+0
* x86: ivybridge: Set up the LPC device using driver modelSimon Glass2016-01-24-1/+5
* x86: Remove HAVE_ACPI_RESUMEBin Meng2015-12-09-9/+0
* x86: Convert to use driver model timerBin Meng2015-12-01-1/+0
* x86: chromebook_link: Enable the debug UARTSimon Glass2015-10-21-0/+7
* x86: ivybridge: Use reset_cpu()Simon Glass2015-04-29-3/+2
* x86: chromebook_link: dts: Add PCH and LPC devicesSimon Glass2015-04-18-1/+1
* dm: x86: pci: Convert chromebook_link to use driver model for pciSimon Glass2015-04-18-7/+9
* x86: Split up arch_cpu_init()Simon Glass2015-04-16-0/+8
* x86: Add a x86_ prefix to the x86-specific PCI functionsSimon Glass2015-04-16-19/+19
* x86: ivybridge: Update microcode early in bootSimon Glass2015-01-13-1/+1
* x86: ivybridge: Drop support for ROM cachingSimon Glass2015-01-13-25/+0
* x86: Add post failure codes for bist and carBin Meng2014-12-13-0/+1
* x86: ivybridge: Add LAPIC supportSimon Glass2014-11-21-0/+3
* x86: ivybridge: Add early init for PCH devicesSimon Glass2014-11-21-0/+141
* x86: ivybridge: Perform Intel microcode update on bootSimon Glass2014-11-21-0/+5
* x86: ivybridge: Check BIST value on bootSimon Glass2014-11-21-0/+16
* x86: ivybridge: Perform initial CPU setupSimon Glass2014-11-21-0/+130
* x86: ivybridge: Add early LPC init so that serial worksSimon Glass2014-11-21-0/+12
* x86: ivybridge: Enable PCI in early initSimon Glass2014-11-21-0/+6
* x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass2014-11-21-0/+2
* x86: Add chromebook_link boardSimon Glass2014-11-21-0/+42
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