Commit message (Expand) | Author | Age | Lines | |
---|---|---|---|---|
* | x86: ivybridge: Allow microcode to be collated | Simon Glass | 2016-08-30 | -1/+11 |
* | x86: Add debugging when a microcode update fails | Simon Glass | 2016-08-30 | -1/+3 |
* | dm: Rename disk uclass to ahci | Simon Glass | 2016-05-17 | -1/+1 |
* | x86: Add common SDRAM-init code | Simon Glass | 2016-03-17 | -0/+272 |
* | x86: Move common PCH code into a common place | Simon Glass | 2016-03-17 | -0/+26 |
* | x86: Update microcode for secondary CPUs | Simon Glass | 2016-03-17 | -0/+2 |
* | x86: Record the CPU details when starting each core | Simon Glass | 2016-03-17 | -1/+6 |
* | x86: Move Intel Management Engine code to a common place | Simon Glass | 2016-03-17 | -0/+305 |
* | x86: Rename PORT_RESET to IO_PORT_RESET | Simon Glass | 2016-03-17 | -2/+2 |
* | x86: Move common CPU code to its own place | Simon Glass | 2016-03-17 | -0/+112 |
* | x86: Move common LPC code to its own place | Simon Glass | 2016-03-17 | -0/+101 |
* | x86: Move microcode code to a common location | Simon Glass | 2016-03-17 | -1/+172 |
* | x86: Move cache-as-RAM code into a common location | Simon Glass | 2016-03-17 | -0/+248 |