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* powerpc/mpc8349: Use generic mpc85xx DDR driverYork Sun2013-12-04-3/+1
| | | | | | | | | | MPC8349 has been using mpc85xx DDR driver through a symbolic link to mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set under driver/ddr/fsl/, the link is replaced by referring driver directly. We now can simply enable the macro and use the driver. Other mpc83xx SoCs still use their own driver. Signed-off-by: York Sun <yorksun@freescale.com>
* T4240: Address T4240/T4160 Rev2.0 DDR clock changeZang Roy-R619112013-12-04-0/+8
| | | | | | | | | MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0. It's 12 in Rev1.0, for Rev2.0 it uses 6. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/corenet: CPC1 speculation disableDave Liu2013-12-04-0/+4
| | | | | | | | | | In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable CPC1 speculation and keep it till relocation. Otherwise, speculation transactions will go to DDR controller, it will cause problem. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Add T2080/T2081 SoC supportShengzhou Liu2013-11-25-1/+419
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* net/fman: Add support for 10GEC3 and 10GEC4Shengzhou Liu2013-11-25-0/+4
| | | | | | | There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* Driver/IFC: Move Freescale IFC driver to a common driverYork Sun2013-11-25-1130/+3
| | | | | | | | Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xxYork Sun2013-11-25-275/+13
| | | | | | | Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-25-8685/+43
| | | | | | | Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
* mpc85xx: Fix the offset of register address errorTang Yuantian2013-11-25-2/+2
| | | | | | | | | The offset of register address within GPIO module is just CONFIG_SYS_MPC85xx_GPIO_ADDR. So, fix it. The following platforms are confirmed: MPC8572, P1023, P1020, P1022, P2020, P4080, P5020, P5040, T4240, B4860. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
* powerpc: mpc824x: Do not create a symbolic link to bedbug_603e.cMasahiro Yamada2013-11-17-6/+1
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc83xx: Do not create a symbolic link to ddr-gen2.cMasahiro Yamada2013-11-17-5/+1
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc83xx: delete unused rulesMasahiro Yamada2013-11-17-6/+0
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: move mpc8xxx entry under arch/powerpc/cpu/Masahiro Yamada2013-11-17-0/+9
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Makefile: make directories by Makefile.buildMasahiro Yamada2013-11-17-6/+0
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc/85xx: fix broken cpu "clock-frequency" propertyLaurentiu TUDOR2013-11-13-2/+3
| | | | | | | | | | | | | | | When indexing freqProcessor[] we use the first value in the cpu's "reg" property, which on new e6500 cores IDs the threads. But freqProcessor[] should be indexed with a core index so, when fixing "the clock-frequency" cpu node property, access the freqProcessor[] with the core index derived from the "reg' property. If we don't do this, last half of the "cpu" nodes will have broken "clock-frequency" values. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: York Sun <yorksun@freescale.com>
* powerpc/t4240: fix per pci endpoint liodn offsetsLaurentiu TUDOR2013-11-13-5/+24
| | | | | | | | | | | | | | | | | | | | | | | Update the code that builds the pci endpoint liodn offset list so that it doesn't overlap with other liodns and doesn't generate negative offsets like: fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf 0xffffffd1 0xffffffd3 0xffffffd5 0xffffffd7 0xffffffd9 0xffffffdb>; The update consists in adding a parameter to the function that builds the list to specify the base liodn. On PCI v2.4 use the old base = 256 and, on PCI 3.0 where some of the PCIE liodns are larger than 256, use a base = 1024. The version check is based on the PCI controller's version register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com>
* powerpc/t4240: set pcie liodn in the correct registerLaurentiu TUDOR2013-11-13-4/+4
| | | | | | | | | | | | The liodn for the T4240's PCIE controller is no longer set through a register in the guts register block but with one in the PCIE register block itself. Use the already existing SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com>
* powerpc/83xx: Define USB1 and USB2 base addr for MPC834xramneek mehresh2013-11-13-0/+5
| | | | | | | Define base addresse for both MPH(USB1) and DR(USB2) controllers for MPC834x socs Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* powerpc/t1040: Update defines to support T1040SoC personalitiesPriyanka Jain2013-11-13-2/+14
| | | | | | | | | | | | | | | | T1040 Soc has four personalities: -T1040 (4 cores with L2 switch) -T1042:Reduced personality of T1040 without L2 switch -T1020:Reduced personality of T1040 with less cores(2 cores) -T1022:Reduced personality of T1040 with 2 cores and without L2 switch Update defines in arch/powerpc header files, Makefiles and in driver/net/fm/Makefile to support all T1040 personalities Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: fixed Makefiles] Acked-by: York Sun <yorksun@freescale.com>
* MPC824x: remove obsolete "PN62" boardWolfgang Denk2013-11-11-4/+2
| | | | | | | | | | | The MPC824x processors have long reached EOL, and the PN62 board has not seen any board-specific updates for more than a decade. It is now causing build issues. Instead of wasting time on things nobody is interested in any more, we rather drop this board. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Wolfgang Grandegger <wg@grandegger.com> cc: Tom Rini <trini@ti.com>
* include: delete include/linux/config.hMasahiro Yamada2013-11-08-12/+0
| | | | | | | | | | | | Linux Kernel abolished include/linux/config.h long time ago. (around version v2.6.18..v2.6.19) We don't need to provide Linux copatibility any more. This commit deletes include/linux/config.h and fixes source files not to include this. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* cosmetic: remove empty lines at the top of fileMasahiro Yamada2013-11-08-5/+0
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-580/+267
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Note: arch/powerpc/cpu/mpc8260/Makefile is originally like follows: ---<snip>--- START = start.o kgdb.o COBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \ ---<snip>--- COBJS-$(CONFIG_ETHER_ON_SCC) = ether_scc.o ---<snip>--- $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o) The link rule `$(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o)' is weird. kbdg.o is not included in $(OBJS) but linked into $(LIB) and $(LIB) is not dependent on kgdb.o. (Broken dependency tracking) So, START = start.o kgdb.o shoud have been START = start.o SOBJS = kgdb.o That is why this commit adds kgdb.o to obj-y, not to extra-y. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de>
* fsl/mpc85xx: define common serdes_clock_to_string functionValentin Longchamp2013-10-24-0/+39
| | | | | | | | | | | | This allows to share some common code for the boards that use a corenet base SoC. Two different versions of the function are available in fsl_corenet_serdes.c and fsl_corenet2_serdes.c files. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix t1040qds.c] Acked-by: York Sun <yorksun@freescale.com>
* mpc8xxx: set x2 DDR3 refresh rate if SPD config requires itValentin Longchamp2013-10-24-1/+17
| | | | | | | | | | | | | | | If the DDR3 module supports industrial temperature range and requires the x2 refresh rate for that temp range, the refresh period must be 3.9us instead of 7.8 us. This was successfuly tested on kmp204x board with some MT41K128M16 DDR3 RAM chips (no module used, chips directly soldered on board with an SPD EEPROM). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix minor conflicts in fsl_ddr_dimm_params.h, lc_common_dimm_params.c, common_timing_params.h] Acked-by: York Sun <yorksun@freescale.com>
* mpc8xxx: call i2c_set_bus_num in __get_spdValentin Longchamp2013-10-24-1/+5
| | | | | | This is necessary with the new I2C subystem that was introduced lately. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* powerpc: cast bi_memsize to ulong for %ld usageValentin Longchamp2013-10-24-1/+1
| | | | | | | | | | When exporting the new memsize without reserved PRAM area, the -Wformat option produces a warning since %ld is used for snprintf and bi_memsize is phys_size_t. This patch removes this warning for all PRAM PowerPC boards. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* powerpc/usb:Differentiate USB controller base addressramneek mehresh2013-10-24-14/+21
| | | | | | | | Introduce different macros for storing addresses of multiple USB controllers. This is required for successful initialization and usage of multiple USB controllers inside u-boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* powerpc/usb:Define CONFIG_USB_MAX_CONTROLLER_COUNT for all 85xx socsramneek mehresh2013-10-24-3/+29
| | | | | | | | CONFIG_USB_MAX_CONTROLLER_COUNT macro recently defined for initializing all USB controllers on a given platform. This macro is defined for all 85xx socs Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2013-10-21-2/+2
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| * usb: add enum usb_init_type parameter to usb_lowlevel_initTroy Kisky2013-10-20-2/+2
| | | | | | | | | | | | This parameter will later be used to verify OTG ports. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* | PCIe:change the method to get the address of a requested capability in ↵Zhao Qiang2013-10-16-18/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
* | powerpc/mpc85xx: Add workaround for erratum A006379York Sun2013-10-16-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com>
* | powerpc: Fix CamelCase warnings in DDR related codePriyanka Jain2013-10-16-464/+464
| | | | | | | | | | | | | | | | | | | | | | Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h has various parameters with embedded acronyms capitalized that trigger the CamelCase warning in checkpatch.pl Convert those variable names to smallcase naming convention and modify all files which are using these structures with modified structures. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
* | powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW acceleratorPrabhakar Kushwaha2013-10-16-60/+89
| | | | | | | | | | | | | | | | | | | | | | CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc/mpc85xx:Update processor defines for T1040Prabhakar Kushwaha2013-10-16-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040 SoC has - DDR controller ver 5.0 - 2 PLLs - 8 IFC Chip select - FMAN Muram 192K - No Srio - Sec controller ver 5.0 - Max CPU update for its personalities So, update the defines accordingly. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2Prabhakar Kushwaha2013-10-16-5/+5
| | | | | | | | | | | | | | | | | | | | CHASSIS2 architecture never defines type of L2 cache present in SoC. it is dependent upon the core present in the SoC. for example, - e6500 core has L2 cluster (Kibo) - e5500 core has Backside L2 Cache Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.hPo Liu2013-10-16-0/+2
|/ | | | | | | This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: Po Liu <Po.Liu@freescale.com>
* Coding Style cleanup: replace leading SPACEs by TABsWolfgang Denk2013-10-14-9/+9
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-14-29/+29
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* SPDX: fix IBM-pibs license identifierWolfgang Denk2013-09-20-9/+9
| | | | | | | | | | | | | The SPDX License List version 1.19 now contains an official entry for the IBM-pibs license. However, instead of our suggestion "ibm-pibs", the SPDX License List uses "IBM-pibs", with the following rationale: "The reason being that all other SPDX License List short identifiers tend towards using capital letters unless spelling a word. I'd prefer to be consistent to this end". Change the license IDs to use the official name. Signed-off-by: Wolfgang Denk <wd@denx.de>
* powerpc/mpc85xx: Add workaround for erratum A-005125York Sun2013-09-10-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | In a very rare condition, a system hang is possible when the e500 core initiates a guarded load to PCI / PCIe /SRIO performs a coherent write to memory. Please refer to errata document for more details. This erratum applies to the following SoCs and their variants, if any. BSC9132 BSC9131 MPC8536 MPC8544 MPC8548 MPC8569 MPC8572 P1010 P1020 P1021 P1022 P1023 P2020 C29x Signed-off-by: York Sun <yorksun@freescale.com> CC: Scott Wood <scottwood@freescale.com>
* powerpc/mpc85xx: Fix the I2C bus speed error on p1022Tang Yuantian2013-09-09-1/+2
| | | | | | | | The source clock frequency of I2C bus on p1022 is the platform(CCB) clock, not CCB/2. The wrong source clock frequency leads to wrong I2C bus speed setting. so, fixed it. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
* SPL: P1022DS: switch to new multibus/multiadapter supportYing Zhang2013-09-09-0/+5
| | | | | | | - Added section "u_boot_list" in arch/powerpc/cpu/mpc85xx/u-boot-spl.lds - Use the function i2c_init_all instead of i2c_init Signed-off-by: Ying Zhang <b40530@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-08-21-175/+202
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| * Fix for incorrect conversion hex string to number (FMAN firmware address).Николай Пузанов2013-08-20-1/+1
| | | | | | | | | | Signed-off-by: Николай Пузанов <punzik@gmail.com> Acked-by: York Sun <yorksun@freescale.com>
| * powerpc/sec: Add workaround for SEC A-003571Shengzhou Liu2013-08-20-1/+14
| | | | | | | | | | | | | | | | | | Multiple read/write transactions initiated by security engine may cause system to hang. Workaround: set MCFGR[AXIPIPE] to 0 to avoid hang. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * powerpc/t4240: add QSGMII interface supportShaohui Xie2013-08-20-7/+7
| | | | | | | | | | | | | | | | | | | | Also some fix for QSGMII. 1. fix QSGMII configure of Serdes2. 2. fix PHY address of QSGMII MAC9 & MAC10 for each FMAN. 3. fix dtb for QSGMII interface. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * powerpcv2: Print hardcoded size like print_size() doesShruti Kanetkar2013-08-20-21/+21
| | | | | | | | | | | | | | | | | | Makes the startup output more consistent Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: York Sun <yorksun@freescale.com>
| * powerpc: Use print_size() where appropriateShruti Kanetkar2013-08-20-22/+21
| | | | | | | | | | | | | | | | Makes the startup output more consistent Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
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