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* | powerpc/8xxx: Fix typo for address hashing messageKumar Gala2011-04-04-1/+1
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | mpc8xxx: DDR2/DDR3: Clean up DIMM-type switch statementsKyle Moffett2011-04-04-33/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The numeric constants in the switch statements are replaced by #defines added to the common ddr_spd.h header. This dramatically improves the readability of the switch statments. In addition, a few of the longer lines were cleaned up, and the DDR2 type for an SO-RDIMM module was added to the DDR2 switch statement. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | fsl_ddr: Don't use full 64-bit divides on 32-bit PowerPCKyle Moffett2011-04-04-16/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit integer divide operations to convert between nanoseconds and DDR clock cycles given arbitrary DDR clock frequencies. Since all of the inputs to this are 32-bit (nanoseconds, clock cycles, and DDR frequencies), we can easily restructure the computation to use the "do_div()" function to perform 64-bit/32-bit divide operations. On 64-bit this change is basically a no-op, because do_div is implemented as a literal 64-bit divide operation and the instruction scheduling works out almost the same. On 32-bit PowerPC a fully accurate 64/64 divide (__udivdi3 in libgcc) is over 1.1kB of code and thousands of heavily dependent cycles to compute, all of which is linked from libgcc. Another 1.2kB of code comes in for the function __umoddi3. It should be noted that nothing else in U-Boot or the Linux kernel seems to require a full 64-bit divide on my 32-bit PowerPC. Build-and-boot-tested on the HWW-1U-1A board using DDR2 SPD detection. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Acked-by: York Sun <yorksun@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Fix setting of LIODN prop in PCIe nodes on P3041/P5020Laurentiu TUDOR2011-04-04-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | We utilize the compatible string to find the node to add fsl,liodn property to. However P3041 & P5020 don't have "fsl,p4080-pcie" compatible for their PCIe controllers as they aren't backwards compatible. Allow the macro's to specify the PCIe compatible to use to allow SoC uniqueness. On P3041 & P5020 we utilize "fsl,qoriq-pcie-v2.2" for the PCIe controllers. Signed-off-by: Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Update timer-frequency prop in ptp_timer node of device treebhaskar upadhaya2011-04-04-0/+9
| | | | | | | | | | | | | | | | | | | | Fix up the device tree property associated with the IEEE 1588 timer source frequency. Currently we only support the IEEE 1588 timer source being the internal eTSEC system clock (for those SoCs with IEEE 1588 support). The eTSEC clock is ccb_clk/2. Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Fix determining Fman freq on P1023Kumar Gala2011-04-04-4/+1
| | | | | | | | | | | | | | | | On the P1023 the Fman freq is equivalent to the system bus freq, not 1/2 of it. Also we only have one Fman so no need for the code to deal with a second. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Fixup determining PME, FMan freqKumar Gala2011-04-04-9/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some additional rules to determining the various frequencies that PME & FMan IP blocks run at. We need to take into account: * Reduced number of Core Complex PLL clusters * HWA_ASYNC_DIV (allows for /2 or /4 options) On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs the PME & FMan blocks utilize the second Core Complex PLL. On SoCs like p4080 with 4 Core Complex PLLs we utilize the third Core Complex PLL for PME & FMan blocks. On P2040/P3041/P5020 we have the added feature that we can divide the PLL down further by either /2 or /4 based on HWA_ASYNC_DIV. On P4080 this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be set to 0 and this gets a backward compatiable /2 behavior. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Specify CONFIG_SYS_FM_MURAM_SIZEKumar Gala2011-04-04-0/+8
| | | | | | | | | | | | | | CONFIG_SYS_FM_MURAM_SIZE varies from SoC to SoC to specify it in config_mpc85xx.h for those parts with a Frame Manager. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Corrected sdhc clock value for P1010Priyanka Jain2011-04-04-1/+2
| | | | | | | | | | | | | | | | SDHC clock is equal to CCB on P1010 and P1014 not CCB/2. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Adds some P1010/P1014 SoC configuration definesPoonam Aggrwal2011-04-04-0/+8
| | | | | | | | | | | | | | | | Add defines for FSL_SATA_V2, # of DDR controllers, reset value of CCSRBAR and SDHC erratum. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Support for Freescale P1024/P1025 processorKumar Gala2011-04-04-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Support for Freescale P1024/P1025 (dual core) and P1015/P1016 (single core) processors. P1024 is a variant of P1020 processor with a core frequency from 400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA P1025 is a variant of P1021 processor with a core frequency from 400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA P1015 is a variant of P1024 processor with single core and P1016 is a variant of P1025 processor with single core. Added comments in config_mpc85xx.h to denote single core versions of processors. Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: load ucode from nand flash before qe_initHaiying Wang2011-04-04-0/+17
| | | | | | | | | | | | | | | | In the case the QE's microcode is stored in nand flash, we need to load it from NAND flash to ddr first then the qe_init can get the ucode correctly. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | fsl_ddr: Adds 16 bit DDR Data width optionPoonam Aggrwal2011-04-04-1/+4
| | | | | | | | | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/8xxx: Display DIMM modelYork Sun2011-04-04-4/+7
| | | | | | | | | | | | | | | | Beside displaying RDIMM or UDIMM, this patch adds display of the model numbers embedded in SPD. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | fsl_pci: Add support for FSL PCIe controllers v2.xPrabhakar Kushwaha2011-04-04-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FSL PCIe controller v2.1: - New MSI inbound window - Same Inbound windows address as PCIe controller v1.x Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window FSL PCIe controller v2.2 and v2.3: - Different addresses for PCIe inbound window 3,2,1 - Exposed PCIe inbound window 0 - New PCIe interrupt status register Added new Interrupt Status register to struct ccsr_pci & updated pit_t array size to reflect the 4 inbound windows. To maintain backward compatiblilty, on V2.2 or greater controllers we start with inbound window 1 and leave inbound 0 with its default value (which maps to CCSRBAR). Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Refactor Qman/Portal support to be shared between SoCsHaiying Wang2011-04-04-22/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Add support for Freescale P1023/P1017 ProcessorsRoy Zang2011-04-04-1/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | Add P1023 (dual core) & P1017 (single core) specific information: * SERDES Table * Added P1023/P1017 to cpu_type_list and SVR list (fixed issue with P1013 not being sorted correctly). * Added P1023/P1027 to config_mpc85xx.h * Added new LAW type introduced on P1023/P1017 * Updated a few immap register/defines unique to P1023/P1017 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Don't build read_tlbcam_entry for CONFIG_NAND_SPLKumar Gala2011-04-04-2/+2
| | | | | | | | | | | | Slim down NAND SPL build a bit as we don't need read_tlbcam_entry. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc: Add cpu_secondary_init_r to allow for initialization post env setupKumar Gala2011-04-04-6/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | We can simplify some cpu/SoC level initialization by moving it to be after the environment and non-volatile storage is setup as there might be dependancies on such things in various boot configurations. For example for FSL SoC's with QE if we boot from NAND we need it setup to extra the ucode image to initialize the QE. If we always do this after environment & non-volatile storage is working we can have the code be the same regardless of NOR, NAND, SPI, MMC boot. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Cleanup some QE related definesKumar Gala2011-04-04-67/+37
| | | | | | | | | | | | | | | | | | Move some processor specific QE defines into config_mpc85xx.h and use QE_MURAM_SIZE to cleanup some ifdef mess in the QE immap struct. Also fixed up some comment style issues in immap_qe.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from boardKumar Gala2011-04-04-3/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards pretty much do the same thing. The only variations are in how many controllers or DIMMs per controller exist. To make this work we standardize on the names of the SPD_EEPROM_ADDRESS defines based on the use case of the board. We allow boards to override get_spd to either do board specific fixups to the SPD data or deal with any unique behavior of how the SPD eeproms are wired up. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()Kumar Gala2011-04-04-6/+3
| | | | | | | | | | | | | | | | | | | | Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq() and every 86xx board uses get_bus_freq(). If implement get_ddr_freq() as a static inline to call get_bus_freq() we can remove fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq() directly. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc: Move cpu specific lmb reserve to arch_lmb_reserveKumar Gala2011-04-04-0/+5
| | | | | | | | | | | | | | | | We've been utilizing board_lmb_reserve to reserve the boot page for MP systems. We can just move this into arch_lmb_reserve for 85xx & 86xx systems rather than duplicating in each board port. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Add some defines for P2040, P3041, P5010, P5020Kumar Gala2011-04-04-0/+15
| | | | | | | | | | | | | | Specify the number of DDR controllers, number of frame managers, number of 1g and 10g ports. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Extend ethernet device tree stashing parameters for "fsl,etsec2"Pankaj Chauhan2011-04-04-0/+3
| | | | | | | | | | | | | | | | | | In a manner similar to passing ethernet stashing parameters into device tree for "gianfar", extend the support to the "fsl,etsec2" as well. Signed-off-by: Pankaj Chauhan <pankaj.chauhan@freescale.com> Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Declare fsl_ddr_set_memctl_regs in <asm/fsl_ddr_sdram.h>Kumar Gala2011-04-04-0/+2
| | | | | | | | | | | | | | | | | | Remove declerations of fsl_ddr_set_memctl_regs in board files with and place it into a common header. Based on patch from Poonam Aggrwal. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Add support for Integrated Flash Controller (IFC)Dipen Dudhat2011-04-04-2/+1056
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Add SERDES support for P1010/P1014Prabhakar Kushwaha2011-04-04-0/+82
|/ | | | | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCsPrabhakar Kushwaha2011-03-29-1/+52
| | | | | | | | | | The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Enable various errata on P1022/P1013 SoCsJiang Yutang2011-03-28-0/+6
| | | | | | | | | | Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on P1022/P1013 SoCs. Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2. Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2011-03-27-40/+40
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| * rename _end to __bss_end__Po-Yu Chuang2011-03-27-40/+40
| | | | | | | | | | | | | | Currently, _end is used for end of BSS section. We want _end to mean end of u-boot image, so we rename _end to __bss_end__ first. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
* | powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134York Sun2011-03-24-0/+41
| | | | | | | | | | | | | | | | The fix for errata workaround is to avoid covering physical address 0xff000000 to 0xffffffff during the implementation. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8xxx: disable rcw_en bit for non-DDR3York Sun2011-03-24-0/+2
| | | | | | | | | | | | | | | | rcw_en bit is only available for DDR3 controllers. It is a reserved bit on DDR1 and DDR2 controllers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8xxx: fix recognition of DIMMs with ECC and Address ParityYork Sun2011-03-24-1/+6
|/ | | | | | | | To recognize DIMMs with ECC capability by testing ECC bit only. Not to be confused by Address Parity bit. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Introduce a new linker flag LDFLAGS_FINALHaiying Wang2011-03-22-1/+1
| | | | | | | | | | | | | | | commit 8aba9dceebb14144e07d19593111ee3a999c37fc Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS breaks the usage of --gc-section to build nand_spl. We still need linker option --gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes the --gc-sections to each uboot image. To get the proper linker flags, we use LDFLAGS and LDFLAGS_FINAL to replace PLATFORM_LDFLAGS in the Makefile of each nand_spl board. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* powerpc/85xx: Fix synchronization of timebase on MP bootKumar Gala2011-03-15-0/+9
| | | | | | | | | | | There is a small ordering issue in the master core in that we need to make sure the disabling of the timebase in the SoC is visible before we set the value to 0. We can simply just read back the value to synchronizatize the write, before we set TB to 0. Reported-by: Dan Hettena Tested-by: Dan Hettena Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc8[5/6]xx: Ensure POST word does not get resetJohn Schmoller2011-03-13-0/+32
| | | | | | | | | | | | The POST word is stored in a spare register in the PIC on MPC8[5/6]xx processors. When interrupt_init() is called, this register gets reset which resulted in all POST_RAM POSTs not being ran due to the corrupted POST word. To resolve this, store off POST word before the PIC is reset, and restore it after the PIC has been initialized. Signed-off-by: John Schmoller <jschmoller@xes-inc.com> Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix plat_mp_up() disabling of BPTR for CoreNet PlatformsEd Swarthout2011-03-05-2/+2
| | | | | | | | Copying directly from ECM/PQ3 is not correct for how CoreNet based platforms handle boot page translation. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registersYork Sun2011-03-05-6/+14
| | | | | | | | | The write recovery time of both registers should match. Since mode register doesn't support cycles of 9,11,13,15, we should use next higher number for both registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3York Sun2011-02-10-1/+4
| | | | | | | | | When DDR data rate is higher than 1200MT/s or controller interleaving is enabled, additional cycle for write-to-read turnaround is needed to satisfy dynamic ODT timing. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2011-02-09-0/+3
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| * ppc4xx: Add DLVision-10G board supportDirk Eibach2011-02-07-0/+3
| | | | | | | | | | | | | | | | | | | | Board support for the Guntermann & Drunck DLVision-10G. Adds support for multiple FPGAs per board for gdsys 405ep architecture. Adds support for dual link osd hardware for gdsys 405ep. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2011-02-06-8/+26
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| * | mpc83xx: Use correct register to calculate clocks.Joakim Tjernlund2011-02-05-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use SPMR instead of HRCWL when calculating clocks as HCRWL may be changed and the CPU will not pick up all changes until there is a POR. u-boot will think SPMF has changed and get the clocks wrong. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | mpc83xx: fix pcie configuration space read/writeLeo Liu2011-02-05-1/+18
| |/ | | | | | | | | | | | | | | | | | | | | | | This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | powerpc/8xxx: Fix possible compile issue related to P1013Kumar Gala2011-02-04-1/+1
| | | | | | | | | | | | | | | | | | The P1013 is a single core version of P1022 and thus should use the p1022_serdes.c code. It was acciently pointing to p1013_serdes.c which doesn't exist. Reported-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc85xx: implement workaround for errata DDR111 and DDR134York Sun2011-02-03-1/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | Workaround for the following errata: DDR111 - MCKE signal may not function correctly at assertion of HRESET DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can calibrate to incorrect values These two workarounds must be implemented together because they touch common registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Rename MPC8572 DDR erratum to DDR115York Sun2011-02-03-2/+5
| | | | | | | | | | | | | | | | Use unique erratum number instead of platform number. Enable command that reports errata on MPC8572DS. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Remove unnecessary polling loop from DDR initYork Sun2011-02-03-2/+0
| | | | | | | | | | | | | | | | This polling loop is not required normally, unless specifically stated in workaround. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-11-13 01:56:51 +0000