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authorPoonam Aggrwal <poonam.aggrwal@freescale.com>2011-02-06 11:31:44 +0530
committerKumar Gala <galak@kernel.crashing.org>2011-04-04 09:24:42 -0500
commit1fbf3483b75f93c86b94439d4e0181d1b0546c92 (patch)
tree03d36198e7779c93560f65d3cc8c7a8d7c8e4d9f /arch/powerpc
parent093cffbe9a692bd6bb47b0775d015545b1628af8 (diff)
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powerpc/85xx: Adds some P1010/P1014 SoC configuration defines
Add defines for FSL_SATA_V2, # of DDR controllers, reset value of CCSRBAR and SDHC erratum. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 040e71b..ac304f3 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -91,6 +91,10 @@
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
/* P1011 is single core version of P1020 */
#elif defined(CONFIG_P1011)
@@ -127,6 +131,10 @@
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
/* P1015 is single core version of P1024 */
#elif defined(CONFIG_P1015)