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* | mpc85xx/t104x: Add deep sleep framework supportTang Yuantian2014-04-22-0/+8
| | | | | | | | | | | | | | | | | | | | When T104x soc wakes up from deep sleep, control is passed to the primary core that starts executing uboot. After re-initialized some IP blocks, like DDRC, kernel will take responsibility to continue to restore environment it leaves before. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/cpu/mpc85xx: Add MAC address for layer 2 switchCodrin Ciubotariu2014-04-22-0/+29
| | | | | | | | | | | | | | | | | | | | | | T1040RDB and T1040QDS boards have an integrated l2 switch. The switch needs a MAC address for Layer 2 protocols (MSTP, LLDP, LACP, etc). Setting a MAC address on l2switchaddr will add a MAC in device-tree, under node l2switch. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Cc: York Sun <yorksun@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: Add workaround for erratum A007212York Sun2014-04-22-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun <yorksun@freescale.com>
* | fsl/usb: Workaround for USB erratum-A007075Nikhil Badola2014-04-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Put a delay of 5 millisecond after reset so that ULPI phy gets enough time to come out of reset. Erratum A007075 applies to following SOCs and their variants, if any P1010 rev 1.0 B4860 rev 1.0, 2.0 P4080 rev 2.0, 3.0 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/85xx: Fix e6500 L2 cache stash IDsScott Wood2014-04-22-4/+8
| | | | | | | | | | | | | | | | The value written to L2CSR1 didn't match the value written to the device tree. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | QE/U-QE: Add U-QE supportZhao Qiang2014-04-22-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and ↵Zhao Qiang2014-04-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_QE_FW_ADDR CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDSAneesh Bansal2014-04-22-6/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDSAneesh Bansal2014-04-22-7/+2
| | | | | | | | | | | | | | | | | | | | Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc8xxx: SECURE BOOT- Disable law 0 for non PBL platformsAneesh Bansal2014-04-22-0/+10
| | | | | | | | | | | | | | | | | | ISBC creates a LAW 0 entry for non PBL platforms, which is not disabled before transferring the control to uboot. The LAW 0 entry has to be disabled. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | PPC 85xx: Add qemu-ppce500 machineAlexander Graf2014-04-22-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For KVM we have a special PV machine type called "ppce500". This machine is inspired by the MPC8544DS board, but implements a lot less features than that one. It also provides more PCI slots and is supposed to be enumerated by device tree only. This patch adds support for the generic ppce500 machine and tries to rely solely on device tree for device enumeration. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | PPC 85xx: Add ELF entry pointAlexander Graf2014-04-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | We want to be able to directly execute the ELF binary without going through the u-boot.bin one. To know where we have to start executing this ELF binary we have to tell the linker where our entry point is. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | PPC: 85xx: Generalize DDR TLB mapping functionAlexander Graf2014-04-22-15/+32
| | | | | | | | | | | | | | | | | | | | The DDR mapping function really is just a generic virtual -> physical mapping function. Generalize it so it can support any virtual starting offset and IO maps just the same. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | PPC: 85xx: Remove IVOR resetAlexander Graf2014-04-22-76/+0
|/ | | | | | | | | | | There is no need to set IVORs to anything but their default values, so let's leave them where they are. Suggested-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> [York Sun: Add back $(obj)start.S section in mpc8572ds/Makefile] Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc: remove MOUSSE board supportMasahiro Yamada2014-04-18-88/+0
| | | | | | | | | | | Enough time has passed since this board was moved to Orphan. Remove. - Remove board/mousse/* - Remove include/configs/MOUSSE.h - Clean-up defined(CONFIG_MOUSSE) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: remove RPXClassic, RPXlite boards supportMasahiro Yamada2014-04-18-13/+1
| | | | | | | | | | | | | Enough time has passed since these boards were moved to Orphan. Remove. - Remove board/RPXlite/* - Remove board/RPXClassic/* - Remove include/configs/RPXlite.h - Remove include/configs/RPXClassic.h - Clean-up defined(CONFIG_RPXCLASSIC) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: remove ADS860, FADS823, FADS850SAR, FADS860T supportMasahiro Yamada2014-04-18-13/+1
| | | | | | | | | | | Enough time has passed since these boards were moved to Orphan. Remove. - Remove include/configs/{ADS860.h,FADS823.h,FADS850SAR.h,FADS860T.h} - Cleanup defined(CONFIG_ADS), defined(CONFIG_MPC823FADS), defined(CONFIG_MPC850SAR), defined(CONFIG_SYS_DAUGHTERBOARD) - Remove the entries from boards.cfg Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: remove MBX and MBX860T boards supportMasahiro Yamada2014-04-18-24/+0
| | | | | | | | | | | Enough time has passed since these boards were moved to Orphan. Remove. - Remove board/mbx8xx/* - Remove include/configs/{MBX.h,MBX860T.h} - Clean-up if defined(CONFIG_MBX) - Move the entries from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc8xx: delete an unused source fileMasahiro Yamada2014-04-17-20/+0
| | | | | | | | | References to the wireless keyboard should also be removed from README.console. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
* kbuild: rename OBJTREE to objtreeMasahiro Yamada2014-03-12-1/+1
| | | | | | | | | | | Prior to Kbuild, $(OBJTREE) was used for pointing to the top of build directory with absolute path. In Kbuild style, $(objtree) is used instead. This commit renames OBJTREE to objtree and delete the defition of OBJTREE. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* kbuild: rename TOPDIR to stctreeMasahiro Yamada2014-03-12-1/+1
| | | | | | | | | | | | Prior to Kbuild, $(TOPDIR) or $(SRCTREE) was used for pointing to the top of source directory. (No difference between the two.) In Kbuild style, $(srctree) is used instead. This commit renames TOPDIR to srctree and delete the defition of TOPDIR. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* usb: create common header virtual root hub descriptorsStephen Warren2014-03-10-196/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many USB host controller drivers contain almost identical copies of the same virtual root hub descriptors. Put these into a common file to avoid duplication. Note that there were some very minor differences between the descriptors in the various files, such as: - USB 1.0 vs. USB 1.1 - Manufacturer/Device ID - Max packet size - String content I assume these aren't relevant. Cc: Thomas Lange <thomas@corelatus.se> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Gary Jennejohn <garyj@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Eric Millbrandt <emillbrandt@coldhaus.com> Cc: Pierre Aubert <p.aubert@staubli.com> Cc: Stefan Roese <sr@denx.de> Cc: Daniel Hellstrom <daniel@gaisler.com> Cc: Denis Peter <d.peter@mpl.ch> Cc: Rodolfo Giometti <giometti@linux.it> Cc: Zhang Wei <wei.zhang@freescale.com> Cc: Mateusz Zalega <m.zalega@samsung.com> Cc: Remy Bohmer <linux@bohmer.net> Cc: Markus Klotzbuecher <mk@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Gary Jennejohn <garyj@denx.de> Cc: C Nauman <cnauman@diagraph.com> Cc: David Müller <d.mueller@elsoft.ch> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Thomas Abraham <t-abraham@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Andrew Murray <amurray@embedded-bits.co.uk> Cc: Matej Frančeškin <matej.franceskin@comtrade.com> Cc: Cliff Cai <cliff.cai@analog.com> Cc: Bryan Wu <cooloney@gmail.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-03-07-0/+135
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| * powerpc/usb: Workaround for erratum-A006261Suresh Gupta2014-03-07-0/+66
| | | | | | | | | | | | | | | | | | | | | | USB spec says that the minimum disconnect threshold should be over 525 mV. However, internal USB PHY threshold value is below this specified value. Due to this some devices disconnect at run-time. Hence, phy settings are tweaked to increased disconnect threshold to be above 525mV by using this workaround. Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/b4860: Add workaround for errata A006384 and A006475Shaveta Leekha2014-03-07-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * 85xx/b4860: Alternate serdes protocols for B4860/B4420poonam aggrwal2014-03-07-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On B4860 and B4420, some serdes protocols can be used with LC VCO as well as Ring VCO options. Addded Alternate options with LC VCO for such protocols. For example protocol 0x2a on srds 1 becomes 0x29 if it is LC VCO. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/b4860qds: Add support to make Aurora work on B4860QDSShaveta Leekha2014-03-07-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | 1) Add new SerDes1 protocols having Aurora in them 2) Add VSC cross point connections for Aurora to work with CPRI and SGMIIs 3) Configure VSC crossbar switch to connect SerDes1 lanes to aurora on board, by checking SerDes1 protocols 4) SerDes1 Refclks have been set properly to make Aurora, CPRI and SGMIIs to work together properly Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc: mpc8260: consolidate CONFIG_MPC8260 and CONFIG_8260Masahiro Yamada2014-03-07-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, CONFIG_MPC8260 and CONFIG_8260 were used mixed-up. All boards with mpc8260 cpu defined both of them: - CONFIG_MPC8260 was defined in board config headers and include/common.h - CONFIG_8260 was defined arch/powerpc/cpu/mpc8260/config.mk We do not need to have both of them. This commit keeps only CONFIG_MPC8260. This commit does: - Delete CONFIG_8260 and CONFIG_MPC8260 definition in config headers and include/common.h - Rename CONFIG_8260 to CONFIG_MPC8260 in arch/powerpc/cpu/mpc8260/config.mk. - Rename #ifdef CONFIG_8260 to #ifdef CONFIG_MPC8260 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
* | ppc4xx: Remove 4xx NAND booting supportStefan Roese2014-03-07-142/+5
|/ | | | | | | | | | | | | | | | | As ppc4xx currently only supports the deprecated nand_spl infrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely. This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tirumala Marri <tmarri@apm.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-02-25-3/+5
|\ | | | | | | | | | | | | With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
| * powerpc/t208x: some update to support t2081Shengzhou Liu2014-02-24-3/+5
| | | | | | | | | | | | | | | | | | | | - fix serdes definition for t2081. - fix clock speed for t2081. - update ids, as CONFIG_FSL_SATA_V2 is needed only for t2080, T2081 has no SATA. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | common: Add get_effective_memsize() to memsize.cYork Sun2014-02-21-3/+0
| | | | | | | | | | | | | | | | | | This function has been around for powerpc. It is used for systems with memory more than CONFIG_MAX_MEM_MAPPED. In case of non-contiguous memory, this feature can limit U-boot to one block without going over the limit. Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | kbuild: use Linux Kernel build scriptsMasahiro Yamada2014-02-19-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | Now we are ready to switch over to real Kbuild. This commit disables temporary scripts: scripts/{Makefile.build.tmp, Makefile.host.tmp} and enables real Kbuild scripts: scripts/{Makefile.build,Makefile.host,Makefile.lib}. This switch is triggered by the line in scripts/Kbuild.include -build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build.tmp obj +build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build obj We need to adjust some build scripts for U-Boot. But smaller amount of modification is preferable. Additionally, we need to fix compiler flags which are locally added or removed. In Kbuild, it is not allowed to change CFLAGS locally. Instead, ccflags-y, asflags-y, cppflags-y, CFLAGS_$(basetarget).o, CFLAGS_REMOVE_$(basetarget).o are prepared for that purpose. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Gerhard Sittig <gsi@denx.de>
* powerpc/mpc85xx: Update serdes protocols for T1040Prabhakar Kushwaha2014-02-03-36/+29
| | | | | | | | | | | | | T1040 has only one SerDes block. so update the code accordingly. Also, add support of SerDes Protocol 0x00, 0x06, 0x40, 0x69 0x85, 0xA7 and 0xAA Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Update LIODNs for T1040poonam aggrwal2014-02-03-36/+0
| | | | | | | | Removed LIODNs for RMAN, RIO, 10G. T1040 has 10 QMAN portals so assigned LIODNs accordingly. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc: mpc5xxx: remove redundant CONFIG_MPC5xxx definitionMasahiro Yamada2014-01-24-2/+0
| | | | | | | We do not have to define CONFIG_MPC5xxx in board config headers (and start.S) because it is defined in arch/powerpc/cpu/mpc5xxx/config.mk. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc86xx: move CONFIG_MPC86xx definition to CPU config.mkMasahiro Yamada2014-01-24-1/+1
| | | | | | | Define CONFIG_MPC86xx in arch/powerpc/cpu/mpc86xx/config.mk because all target boards with mpc86xx cpu define it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc85xx: move CONFIG_MPC85xx definition to CPU config.mkMasahiro Yamada2014-01-24-1/+1
| | | | | | | Define CONFIG_MPC85xx in arch/powerpc/cpu/mpc85xx/config.mk because all target boards with mpc85xx cpu define it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc5xx: remove redundant CONFIG_5xx definitionMasahiro Yamada2014-01-24-2/+0
| | | | | | | We do not have to define CONFIG_5xx in a source file because it is defined in arch/powerpc/cpu/mpc5xx/config.mk. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc8xx: remove redundant CONFIG_8xx definitionMasahiro Yamada2014-01-24-4/+0
| | | | | | | We do not have to define CONFIG_8xx in source files because it is defined in arch/powerpc/cpu/mpc8xx/config.mk Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: delete unused header filesMasahiro Yamada2014-01-24-141/+0
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Remove obsolete _LINUX_CONFIG_H macroMasahiro Yamada2014-01-24-18/+0
| | | | | | | | | Commit 643aae1406c93ddc64fcf8c136b47cdffd9c8ccd deleted include/linux/config.h but missed to delete _LINUX_CONFIG_H macro. It is no longer used at all. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc:mpc85xx: Add ifc nand boot support for TPL/SPLPo Liu2014-01-21-7/+8
| | | | | | | | | | | | | | | Using the TPL method for nand boot by sram was already supported. Here add some code for mpc85xx ifc nand boot. - For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec. - Use a clear function name for nand spl boot. - Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c in spl/Makefile; Signed-off-by: Po Liu <Po.Liu@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Fix a typo in workaround message for DDR erratum A003474York Sun2014-01-21-1/+1
| | | | | | Unfortunately a typo presents "DDR-A003473" instead of "DDR-A003474". Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/83xx: Add support for get_svr() for 83xx devicesRamneek Mehresh2014-01-21-0/+5
| | | | | | | Defines get_svr() for 83xx devices Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Add support for single source clockingPriyanka Jain2014-01-02-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
* Makefile: Select objects by CONFIG_ rather than $(ARCH) or $(CPU)Masahiro Yamada2013-12-16-7/+5
| | | | | | | | | | | | | | | | | Convert like follows: CPU mpc83xx -> CONFIG_MPC83xx CPU mpc85xx -> CONFIG_MPC85xx CPU mpc86xx -> CONFIG_MPC86xx CPU mpc5xxx -> CONFIG_MPC5xxx CPU mpc8xx -> CONFIG_8xx CPU mpc8260 -> CONFIG_8260 CPU ppc4xx -> CONFIG_4xx CPU x86 -> CONFIG_X86 ARCH x86 -> CONFIG_X86 ARCH powerpc -> CONFIG_PPC Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* PowerPC: merge commonly-defined flagsMasahiro Yamada2013-12-13-37/+12
| | | | | | | | | | PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -ffixed-r2 were defined in all arch/powerpc/${CPU}/config.mk. This commit moves them to arch/powerpc/config.mk. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc/t4240: Add a frequency setting case for fman1Shaohui Xie2013-12-11-0/+3
| | | | | | | A new valid setting case added for fman1, it uses platform frequency. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8349: Use generic mpc85xx DDR driverYork Sun2013-12-04-3/+1
| | | | | | | | | | MPC8349 has been using mpc85xx DDR driver through a symbolic link to mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set under driver/ddr/fsl/, the link is replaced by referring driver directly. We now can simply enable the macro and use the driver. Other mpc83xx SoCs still use their own driver. Signed-off-by: York Sun <yorksun@freescale.com>