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| author | Po Liu <po.liu@freescale.com> | 2014-01-10 10:10:58 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-01-21 13:42:01 -0800 |
| commit | 6609916efb74724e53db368dd48bfb290d4d9f4c (patch) | |
| tree | b3fabb33b4de7f9db70eaa148d760bcb5416f193 /arch/powerpc/cpu | |
| parent | 76356eb57cdf607d4e77dd57cd0449d7f5b7bdab (diff) | |
| download | u-boot-imx-6609916efb74724e53db368dd48bfb290d4d9f4c.zip u-boot-imx-6609916efb74724e53db368dd48bfb290d4d9f4c.tar.gz u-boot-imx-6609916efb74724e53db368dd48bfb290d4d9f4c.tar.bz2 | |
powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
Using the TPL method for nand boot by sram was already
supported. Here add some code for mpc85xx ifc nand boot.
- For ifc, elbc, esdhc, espi, all need the SPL without
section .resetvec.
- Use a clear function name for nand spl boot.
- Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
in spl/Makefile;
Signed-off-by: Po Liu <Po.Liu@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index bc13267..acaa093 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -57,7 +57,14 @@ SECTIONS . = ALIGN(8); __init_begin = .; __init_end = .; -/* FIXME for non-NAND SPL */ + +/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ +#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC + .bootpg ADDR(.text) - 0x1000 : + { + KEEP(*(.bootpg)) + } :text = 0xffff +#else #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ .bootpg ADDR(.text) + 0x1000 : { @@ -69,12 +76,6 @@ SECTIONS #else #error unknown NAND controller #endif -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg ADDR(.text) - 0x1000 : - { - KEEP(*(.bootpg)) - } :text = 0xffff -#else .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : { KEEP(*(.resetvec)) } = 0xffff |