summaryrefslogtreecommitdiff
path: root/arch/mips/lib/cache_init.S
Commit message (Expand)AuthorAgeLines
* MIPS: Ensure cache ops complete in mips_cache_resetPaul Burton2016-09-21-0/+2
* MIPS: Clear hazard between TagLo writes & cache opsPaul Burton2016-09-21-0/+1
* MIPS: Join the coherent domain when a CM is presentPaul Burton2016-09-21-0/+38
* MIPS: L2 cache supportPaul Burton2016-09-21-5/+178
* MIPS: Define register names for cache initPaul Burton2016-09-21-19/+23
* MIPS: Enable use of the instruction cache earlierPaul Burton2016-09-21-0/+13
* MIPS: Split I & D cache line size configPaul Burton2016-05-31-2/+2
* MIPS: Move cache sizes to KconfigPaul Burton2016-05-31-3/+3
* MIPS: Use unchecked immediate addition/subtractionPaul Burton2016-05-21-1/+1
* MIPS: sync processor and register definitions with linux-4.4Daniel Schwierzeck2016-01-16-8/+8
* MIPS: clear TagLo select 2 during cache initPaul Burton2015-01-29-2/+8
* MIPS: allow systems to skip loads during cache initPaul Burton2015-01-29-6/+13
* MIPS: inline mips_init_[id]cache functionsPaul Burton2015-01-29-58/+28
* MIPS: refactor cache loops to a macroPaul Burton2015-01-29-17/+13
* MIPS: refactor L1 cache config reads to a macroPaul Burton2015-01-29-56/+41
* MIPS: unify cache initialization codePaul Burton2015-01-29-0/+277
generated by cgit v1.1 at 2024-10-17 21:49:30 +0000