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* consolidate mdelay by providing a common function for all usersAnatolij Gustschin2011-10-22-1/+0
| | | | | | | | | There are several mdelay() definitions in the driver and board code. Remove them all and provide a common mdelay() in lib/time.c. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Mike Frysinger <vapier@gentoo.org>
* MIPS: mips32: fix wrong loop bound in flush_cache()Yao Cheng2011-09-03-0/+4
| | | | | | | | | | | The issue is found when calling flush_cache() with zero "size" argument. The bound of loop is miscalculated in this case and flush_cache() enters a wrong flushing loop. Signed-off-by: Yao Cheng <saturdaycoder@gmail.com> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Sergei Shtylyov <sshtylyov@mvista.com> Cc: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* MIPS: make cache operation mode configurableDaniel Schwierzeck2011-07-31-1/+5
| | | | | | | | | | | Currently the cache operation mode is hard-coded to CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs which operate at a different mode. This patch makes the cache operation mode configurable via board config. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* MIPS: rename INFINEON_EBU_BOOTCFG to CONFIG_SYS_XWAY_EBU_BOOTFGDaniel Schwierzeck2011-07-31-3/+10
| | | | | | | | | This define is a board-specific config option and should be renamed to follow the U-Boot naming convention. Additionally, add an explaining comment for this option. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* Timer: Remove reset_timer() for non-Nios2 archesGraeme Russ2011-07-26-6/+0
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* Timer: Remove set_timer completelyGraeme Russ2011-07-26-6/+0
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* MIPS: Move timer code to arch/mips/cpu/$(CPU)/Shinya Kuribayashi2011-05-10-1/+99
| | | | | | | | | | | | | | Current timer routines (arch/mips/lib/timer.c) are implemented assuming that MIPS32 coprocessor (CP0) resources, Counter and Compare registers in this case, are available. But this doesn't always work. We need to make sure that all MIPS-based systems don't necessarily use CP0 counter/compare registers as time keeping resources. And some MIPS variant processors might come with different hardware specs with genuine MIPS32 CP0 registers. With this change, each $(CPU)/ directory can have its own timer code. Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* MIPS: Coding style cleanups on common assembly filesShinya Kuribayashi2011-05-07-107/+93
| | | | | | | | | | Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* MIPS: Remove mips_cache_lock() featureShinya Kuribayashi2011-05-07-100/+0
| | | | | | | | | As requested in commit e1390801a3c1a2b6d12fa90be368efc19f5b9bfd ([MIPS] Request for the 'mips_cache_lock()' removal), such feature is no longer needed for current MIPS implementation of U-Boot, and no one in the tree uses it for years. Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* MIPS: Au1x00: Move all Au1x00 specific code to separate subdirectoryDaniel Schwierzeck2011-04-02-2/+69
| | | | | | | | | Au1x00 is a SoC and its specific code should reside in an own SoC subdirectory. Also add -mtune=4kc flag for CPU optimization. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Thomas Lange <thomas@corelatus.se> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* MIPS: IncaIP: Move all IncaIP specific code to separate subdirectoryDaniel Schwierzeck2011-04-02-2/+70
| | | | | | | | | IncaIP is a SoC and its specific code should reside in an own SoC subdirectory. Also add -mtune=4kc flag for CPU optimization. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* MIPS: Optimize the setup of CPU optimization flagsDaniel Schwierzeck2011-04-02-7/+8
| | | | | | | | | | | | | | | | | The current MIPS CPU config.mk code always expects a MIPS 4kc core. This is not appropiate for other CPUs and SoCs. Replace the current MIPSFLAGS code by cc-option macro and use -march=mips32r2 as default optimization level for all MIPS32 CPUs. Note: Since commit f62fb99941c625605aa16a0097b396a5c16d2c88 all toolchains with binutils prior to v2.16 are not working anymore. As agreed with Shinya Kuribayashi the support for those toolchains will be dropped officially with this patch. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* MIPS: Move content of arch/mips/cpu to arch/mips/cpu/mips32Daniel Schwierzeck2011-04-02-0/+4187
All current CPUs and SoCs are based on MIPS32 arch. The complete code resides in the global arch/mips/cpu directory. This is not suitable if other MIPS architectures like MIPS64 or Octeon should be supported in the future. To achieve this the current CPU code is moved to its own mips32 subdirectory. All MIPS32 boards have to use mips32 as config switch in board.cfg. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Thomas Lange <thomas@corelatus.se> Cc: Vlad Lungu <vlad.lungu@windriver.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
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