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* omap3: Add a few comments to "#endif"s for readability.Robert P. J. Day2012-12-10-4/+4
| | | | | | | No functional changes, just more comments for readability when a preprocessor check spans more than a few lines, and for consistency. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* Pass sdrc timing values through board_sdrc_timings structurePeter Barada2012-12-10-22/+27
| | | | | | | | | Instead of passing individual registers by value to board_get_mem_timings, pass a board_mem_timings structure pointer for the board files to fill in. Pass same structure pointer to write_sdrc_timings. This saves about 90 bytes of space in SPL. Signed-off-by: Peter Barada <peter.barada@logicpd.com>
* am33xx: add ELM supportMansoor Ahamed2012-12-10-0/+311
| | | | | | | | | AM33XX has Error Location Module (ELM) that can be used in conjuction with GPMC controller to implement BCH codes fully in hardware. This code is mostly taken from arago tree. Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com> Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* am33xx: NAND supportIlya Yanok2012-12-10-0/+370
| | | | | | | | TI AM33XX has the same GPMC controller as OMAP3 so we could just use the existing omap_gpmc driver. This patch adds adds required definitions/intialization. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* OMAP: include sys_proto.h from boot-commonIlya Yanok2012-12-10-0/+1
| | | | | | | Include asm/arch/sys_proto.h for gpmc_init prototype. Without this we get a warning while building for AM335x. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* omap3/mem.c: remove unused definesAndreas Bießmann2012-12-10-14/+0
| | | | | | | | These GPMC_CS defines are a leftover from prior gpmc_init(). Commit 187af954 removed the need for these definitions but missed to remove them. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2012-11-25-33/+15
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| * mx28: Fix typo in POWER_DCLIMITS_NEGLIMIT_OFFSETMarek Vasut2012-11-24-1/+1
| | | | | | | | | | | | | | | | | | The POWER_DCLIMITS_NEGLIMIT_OFFSET bit in mx28 power supply block is not called POWER_DCLIMITS_NETLIMIT_OFFSET, but POWER_DCLIMITS_NEGLIMIT_OFFSET. Correct the name in the header file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * mx28: Fix typo in POWER_MINPWR_VBG_OFFMarek Vasut2012-11-24-1/+1
| | | | | | | | | | | | | | | | | | The POWER_MINPWR_VBG_OFF bit in mx28 power supply block is not called POWER_MINPWR_FBG_OFF, but POWER_MINPWR_VBG_OFF. Correct the name in the header file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * mx5: Mark lowlevel_init board-specific codeBenoît Thébaudeau2012-11-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The mx5 lowlevel_init.S contains board-specific code based on the reference design. Let's keep it since it avoids creating new lowlevel_init files and it may be used by many boards. But add a config to make it optional in order not to cause issues on boards not following this part of the reference design. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Matt Sealey <matt@genesi-usa.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * mx6: clock: Only show CSPI clock if CSPI is enabledFabio Estevam2012-11-19-0/+2
| | | | | | | | | | | | | | | | | | If a board does not enable CSPI, there is no need to show the CSPI clock frequency as part of the 'clock' command. Reported-by: Dirk Behme <dirk.behme@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Dirk Behme <dirk.behme@gmail.com>
| * mx5: Print CSPI clock in 'clock' commandFabio Estevam2012-11-19-1/+3
| | | | | | | | | | | | Print CSPI clock in 'clock' command. Signed-off-by: Fabio Estevam <festevam@gmail.com>
| * mx5: Align SPI CS naming with i.MX53 reference manualFabio Estevam2012-11-19-3/+3
| | | | | | | | | | | | Align SPI chip select naming with i.MX53 reference manual. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ehci-mxc: Add support for i.MX35Benoît Thébaudeau2012-11-16-0/+2
| | | | | | | | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * ehci-mxc: Define host offsetsBenoît Thébaudeau2012-11-16-0/+2
| | | | | | | | | | | | | | | | | | | | Some MXC SoCs like the i.MX35 have hosts located at unusual offsets, so prepare to the introduction of i.MX35 support by defining the ehci-mxc hosts offsets at SoC level. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * mx31: Move EHCI definitions to ehci-fsl.hBenoît Thébaudeau2012-11-16-26/+0
| | | | | | | | | | | | | | | | | | The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to ehci-fsl.h so that all MXC SoCs can use them. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* | arm: Add control over cachability of memory regionsSimon Glass2012-11-19-11/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra: Add SOC support for display/lcdWei Ni2012-11-19-0/+1107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the LCD peripheral at the Tegra2 SOC level. A separate LCD driver will use this functionality to configure the display. Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Mayuresh Kulkarni: - changes to remove bitfields and clean up for submission Signed-off-by: Simon Glass <sjg@chromium.org> Simon Glass: - simplify code, move clock control into here, clean-up Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra: Add support for PWMSimon Glass2012-11-19-0/+177
| | | | | | | | | | | | | | | | The pulse width/frequency modulation peripheral supports generating a repeating pulse. It is useful for controlling LCD brightness. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra: fdt: Add LCD definitions for TegraSimon Glass2012-11-19-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add LCD definitions and also a proposed binding for LCD displays. The PWM is as per what will likely be committed to linux-next soon. The displaymode binding comes from a proposal here: http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html The panel binding is new, and fills a need to specify the panel timings and other tegra-specific information. Should a binding appear that allows the pwm to handle this automatically, we can revisit this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra: fdt: Add pwm binding and nodeSimon Glass2012-11-19-0/+7
| | | | | | | | | | | | | | | | | | This binding will apparently soon be in linux-next. Bring it in now since we need to do something, and may as well try to target what Linux will have. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra: Add display support to funcmuxSimon Glass2012-11-19-0/+37
| | | | | | | | | | | | | | Add support for a default pin mapping for display1. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra: Use const for pinmux_config_pingroup/table()Simon Glass2012-11-19-4/+4
| | | | | | | | | | | | | | | | | | These two functions don't actually modify their arguments so add a const keyword. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | SPI: Add SPI Driver for EXYNOS.Rajeshwari Shinde2012-11-15-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SPI driver for EXYNOS. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Acked-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: jy0922.shim@samsung.com Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS5: Add base address for SPIHatim RV2012-11-15-0/+6
| | | | | | | | | | | | | | | | | | Add base address definition for SPI device on Exynos. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS: Add clock for SPIHatim RV2012-11-15-0/+126
| | | | | | | | | | | | | | | | | | | | | | Add api to calculate and set the clock for SPI channels Signed-off-by: James Miller <jamesmiller@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS5: Add pinmux support for SPIRajeshwari Shinde2012-11-15-0/+56
| | | | | | | | | | | | | | | | | | This patch adds pinmux support for SPI channels Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS: Add clock for I2SRajeshwari Shinde2012-11-15-0/+153
| | | | | | | | | | | | | | | | | | This patch adds clock support for I2S Signed-off-by: R. Chandrasekar <rcsekar@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS: Add I2S base addressRajeshwari Shinde2012-11-15-0/+3
| | | | | | | | | | | | | | | | | | This patch adds base address for I2S Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Chander Kashyap <chander.kashyap@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS: Add pinmux for I2SRajeshwari Shinde2012-11-15-0/+14
| | | | | | | | | | | | | | | | This patch adds pinmux support for I2S1 Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS: Add parameters required by I2SRajeshwari Shinde2012-11-15-0/+44
| | | | | | | | | | | | | | | | | | This patch adds the audio parameters required by the I2S to play the predefined audio data. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS: Add I2S registersRajeshwari Shinde2012-11-15-0/+66
| | | | | | | | | | | | | | | | | | This patch add I2S registers Signed-off-by: R. Chandrasekar <rcsekar@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | ARM: arm1176: Define arch_cpu_init() for s3c64xxAshok Kumar Reddy2012-11-15-1/+27
| | | | | | | | | | | | | | | | arch_cpu_init() is removed from cpu level to SOC level for arm1176 in commit 4ea6d6b,the same is done for s3c64xx Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | dm: wdt: Move s5p watchdog timer to drivers/watchdog/Marek Vasut2012-11-15-60/+0
| | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: David Müller <d.mueller@elsoft.ch> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS: Clock: Add common function for pll rate calculationMinkyu Kang2012-11-15-64/+38
| | | | | | | | | | | | | | | | Moved the common code to calculate pll clock rate to new function exynos_get_pll_clk(). Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
* | ARCH: EXYNOS: add support to match product idMinkyu Kang2012-11-15-0/+9
| | | | | | | | | | | | | | | | Based upon single SoC there can be multiple variants. This patch add support to match the complete product ID. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
* | arm:exynos4:pinmux: Modify the gpio function for mmcPiotr Wilczek2012-11-15-0/+59
| | | | | | | | | | | | | | | | | | This patch add pinmux settings for Exynos4 for mmc0 and mmc2 Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | gpio:fix: Proper handling of GPIO subsystem parts at Samsung devicesŁukasz Majewski2012-11-15-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now proper GPIO parts numbering is handled at Samsung devices. This fix is necessary for code using GPIO located at other banks than first. Test HW: - Exynos4210 - Trats - S5PC110 - goni Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | arm1136: Fix enable_caches()Benoît Thébaudeau2012-11-10-10/+12
|/ | | | | | | | enable_caches() did not enable icache if CONFIG_SYS_ICACHE_OFF was not defined but CONFIG_SYS_DCACHE_OFF was. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* arch-mx6: add mx6dl_pins.hTroy Kisky2012-11-10-0/+149
| | | | | | | Only the values used in the sabrelite board are added currently. Add more as other boards use them. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* imx-common: cpu: add imx_ddr_sizeTroy Kisky2012-11-10-0/+52
| | | | | | | | | | Read memory setup registers to determine size of available ram. This routine works for mx53/mx6x I need this because when mx6solo called get_ram_size with a too large maximum size, the system hanged. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololiteTroy Kisky2012-11-10-17/+51
| | | | | | | | | | Previously, the same value was returned for both mx6dl and mx6solo. Check number of processors to differeniate. Also, a freescale patch says that sololite has its cpu/rev stored at 0x280 instead of 0x260. I don't have a sololite to verify. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* Merge git://git.denx.de/u-bootStefano Babic2012-11-10-7077/+548
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| * Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-11-05-272/+1435
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| | * socfpga/spl: Remove malloc.hVikram Narayanan2012-11-04-1/+0
| | | | | | | | | | | | | | | | | | Remove unused header Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
| | * socfpga/spl: Remove timer_init from spl_board_initVikram Narayanan2012-11-04-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Timer is initialized already in board_init_r function in (common/spl/spl.c) No need to initialize it again Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Cc: Dinh Nguyen <dinguyen@altera.com>
| | * Merge remote-tracking branch 'u-boot-ti/master'Albert ARIBAUD2012-11-03-13/+59
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| | | * omap3: Rework board.c for !CONFIG_SYS_L2CACHE_OFFTom Rini2012-10-30-13/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_SYS_L2CACHE_OFF is defined we end up with a few warnings currently. Re-order functions so that we don't have that anymore. Signed-off-by: Tom Rini <trini@ti.com>
| | | * arm bootm: Allow to pass board specified atagsPali Rohár2012-10-30-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | Board can implement function setup_board_tags which is used for adding atags Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
| | | * am33xx: Enable UART{1,2,3,4,5} clocksAndrew Bradford2012-10-25-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If configured to use UART{1,2,3,4,5} such as on the Beaglebone RS232 cape or the am335x_evm daughterboard, enable the required clocks for the UART in use. Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
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