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* ENGR00320350 iMX6SLEVK: Fix build warning of PCIE Phy power downYe.Li2015-04-29-0/+2
| | | | | | | | | | | | | | Since the iMX6SL does not have PCIE module, should not define the function "imx_set_pcie_phy_power_down" for it. Otherwise, get the build warning below: arch/arm/cpu/armv7/mx6/soc.c:446:13: warning: 'imx_set_pcie_phy_power_down' defined but not used [-Wunused-function] static void imx_set_pcie_phy_power_down(void) Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 987c48c07c9ef62fa3fe55faa6f7369b30637127) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ENGR00319965 pcie: mask the imx6sl outRichard Zhu2015-04-29-2/+7
| | | | | | | | | imx6sl doesn't have the pcie module, mask the pcie related codes from imx6sl. Signed-off-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit acaff11da33f8f0cb1521d3c48e64e7ed9a87bec) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ENGR00319415 pcie: random link down issue after warm-rstRichard Zhu2015-04-29-0/+18
| | | | | | | | | | | | | | | | | | | There are about 0.02% percentage on some imx6q/dl/solo hw boards, random pcie link down when warm-reset is used. Make sure to clear the ref_ssp_en bit16 of gpr1 before warm-rst, and set ref_ssp_en after the pcie clks are stable to workaround it. rootcause: * gpr regisers wouldn't be reset by warm-rst, while the ref_ssp_en is required to be reset by pcie. (work-around in u-boot) * ref_ssp_en should be set after pcie clks are stable. (work-around in kernel) Signed-off-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit 5cc825b12c6b86a22f1a6a0535b52cf3ee142e77) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ENGR00315894-77 mx6 soc: Add vadc power up/down functionYe.Li2015-04-29-0/+59
| | | | | | | | | | | | Add vadc power up/down function. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 96d990ef754a879f6ca9da4adf6e0be3d21cdc51) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Conflicts: arch/arm/include/asm/arch-mx6/imx-regs.h
* ENGR00315894-76 mx6 clock: Add vadc clock enable functionYe.Li2015-04-29-0/+11
| | | | | | | | | | | | | Add vadc clock enable function. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 721c7a1448c5b7265b597b83d18f8338a27ea213) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Conflicts: arch/arm/cpu/armv7/mx6/clock.c arch/arm/include/asm/arch-mx6/clock.h
* ENGR00315894-71 iMX6SX Update registers and clock for displayYe.Li2015-04-29-0/+445
| | | | | | | | | | | | | Add registers and clock functions to enable/set LCDIF clock and LVDS. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit ef9d769f9ad1b504a1df8b987d269df9944d8e0c) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Conflicts: arch/arm/include/asm/arch-mx6/clock.h arch/arm/include/asm/arch-mx6/crm_regs.h arch/arm/include/asm/arch-mx6/imx-regs.h
* ENGR00315894-57 iMX6SX: Add M4 boot support at soc levelYe.Li2015-04-29-0/+29
| | | | | | | | | | | Implement the override function "arch_auxiliary_core_up" to boot Cortex-M4 by executing command "bootaux". The parameter "boot_private_data" points to fields where stores the stack address and PC address for M4 to run. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 98c15deb3083d5dac7900c58e95f2ac2f422a4d3) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-3 iMX6SX/SL: Modify SOC to support two ENETPeng Fan2015-04-29-6/+48
| | | | | | | | | | | | | | | | | | | iMX6SX has different enet system clocks with iMX6SL, and has two ENET controllers. So update clocks and soc APIs accordingly to support this features. 1. Enet RGMII TX clock source may come from external or internal PLL. By default, use the external phy CLK_25M output as TX clock source. When using internal PLL as source, the function enable_fec_anatop_clock must be called to enable clock for each enet controller. 2. Modify the MAC address function "imx_get_mac_from_fuse" to get either ENET MAC address. 3. Add configuration "CONFIG_FEC_MXC_25M_REF_CLK" to enable ENET 25Mhz reference clock. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ENGR00315894-11 i.mx6:shutdown vddpu and pcie phy to save powerYe.Li2015-04-29-0/+31
| | | | | | | | | | | | | shutdown vddpu and pcie phy to save power Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 580011f86caf137d59a487694f6f7da042164e05) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Conflicts: arch/arm/cpu/armv7/mx6/soc.c
* MLK-10774-2 HDMI: splash screen function enhancementPeng Fan2015-04-29-1/+11
| | | | | | | | | | | | | | -Change HDMI video mode to VGA. -Add pixel clock fraction part setting in IPU driver, fix video mode timing issue. -Add overflow state clear workaround, fix kernel hang in HDMI driver issue. -Correct IPU clock to 264MHz. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 45d532a0237f5baf2ec95b4364ec5bc94d312689) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-1 imx: LDO: add LDO bypassPeng Fan2015-04-29-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | This patch is from two commits: 1. 748eac71fde78aa0c2e8cb3a3bab94bd994c06f5 ENGR00315499-5: Support i.MX6 1.2GHz via LDO bypass Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz, enable LDO bypass and setup PMIC voltages. LDO bypass is dependent on the flatten device tree file. 2. 93d457e4c601ee5266bc30b7dfa5fa1bbfa8500a MLK-9891-1: ARM: imx6: split WDOG_B setting from set_anatop_bypass() function We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to reboot whole board, so split these code to independent function so that board file can call it freely. Board code is not included, board ldo bypass code will be in bsp update code. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* break build if it would produce broken binaryPavel Machek2015-04-13-0/+4
| | | | | | | Add an error in known-bad case so that we don't produce broken and hard to debug binaries. Signed-off-by: Pavel Machek <pavel@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-04-13-0/+33
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| * ARM: mx5: add support for USB armory boardAndrej Rosano2015-04-09-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Inverse Path USB armory board, an open source flash-drive sized computer based on Freescale i.MX53 SoC. http://inversepath.com/usbarmory Signed-off-by: Andrej Rosano <andrej@inversepath.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Chris Kuethe <chris.kuethe@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Vagrant Cascadian <vagrant@debian.org> Tested-By: Vagrant Cascadian <vagrant@debian.org> Tested-by: Chris Kuethe <chris.kuethe@gmail.com>
| * ARM: mx5: move to a standard arch/board approachAndrej Rosano2015-04-09-0/+22
| | | | | | | | | | | | | | | | | | | | Move the MX5 based boards to arch/arm/cpu/armv7/mx5, following the commit: 89ebc82137bebb11a8191f8b9cbf08f2533ae8bc Signed-off-by: Andrej Rosano <andrej@inversepath.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Vagrant Cascadian <vagrant@debian.org> Tested-by: Chris Kuethe <chris.kuethe@gmail.com>
* | ARM: rpi: add a couple more revision IDsStephen Warren2015-04-13-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | According to Gordon Henderson's WiringPi library, there are some more Pi revision IDs out there. Add support for them. http://git.drogon.net/?p=wiringPi;a=blob_plain;f=wiringPi/wiringPi.c;hb=5edd177112c99416f68ba3e8c6c4db6ed942e796 At least ID 0x13 is out in the wild: Reported-by: Chee-Yang Chau <cychau@gmail.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | ARM: fix arch/arm/Makefile for TegraMasahiro Yamada2015-04-11-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 79d75d752717 (ARM: move -march=* and -mtune= options to arch/arm/Makefile), all the Tegra boards are broken because the SPL is built for ARMv7. Insert Tegra-specific code to arch/arm/Makefile to set compiler flags for an earlier ARM architecture. Note: The v1 patch for commit 79d75d752717 *was* correct when it was submitted. Notice it was originally written for multi .config configuration where Kconfig set CONFIG_CPU_V7/CONFIG_CPU_ARM720T for Tegra U-Boot Main/SPL, respectively. But, until it was merged into the mainline, commit e02ee2548afe (kconfig: switch to single .config configuration) had been already applied there. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Stephen Warren <swarren@nvidia.com> Reported-by: Jan Kiszka <jan.kiszka@siemens.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
* | arm: armada-xp: Fix SPL for AXP by using save_boot_params_retStefan Roese2015-04-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | Patch e11c6c27 (arm: Allow lr to be saved by board code) introduced a different method to return from save_boot_params(). The SPL support for AXP has been pulled and changing to this new method is now required for SPL to work correctly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | lpc32xx: add support for board work_92105Albert ARIBAUD \(3ADEV\)2015-04-10-1/+215
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Work_92105 from Work Microwave is an LPC3250- based board with the following features: - 64MB or 128MB SDR DRAM - 1 GB SLC NAND, managed through MLC controller. - Ethernet - Ethernet + PHY SMSC8710 - I2C: - EEPROM (24M01-compatible) - RTC (DS1374-compatible) - Temperature sensor (DS620) - DACs (2 x MAX518) - SPI (through SSP interface) - Port expander MAX6957 - LCD display (HD44780-compatible), controlled through the port expander and DACs This board has SPL support, and uses the LPC32XX boot image format. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* | lpc32xx: add LPC32xx SSP support (SPI mode)Albert ARIBAUD \(3ADEV\)2015-04-10-0/+18
| | | | | | | | | | Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* | lpc32xx: add GPIO supportAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+48
| | | | | | | | | | | | This driver only supports Driver Model, not legacy model. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* | lpc32xx: i2c: add LPC32xx I2C interface supportAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+18
| | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* | lpc32xx: mtd: nand: add MLC NAND controllerAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+11
| | | | | | | | | | | | | | | | | | | | The controller's Reed-Solomon ECC hardware is used except of course for raw reads and writes. It covers in- and out-of-band data together. The SPL framework is supported. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* | lpc32xx: add Ethernet supportAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+20
| | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* | Merge branch 'u-boot/master'Albert ARIBAUD2015-04-10-346/+512
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| * | am33xx/ddr.c: Fix regression on DDR2 platformsTom Rini2015-04-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Back in fc46bae a "clean up" was introduced that intended to reconcile some of the AM335x codepaths based on how AM43xx operates. Unfortunately this introduced a regression on the DDR2 platforms. This was un-noticed on DDR3 (everything except for Beaglebone White) as we had already populated sdram_config correctly in sequence. This change brings us back to the older behavior and is fine on all platforms. Tested on Beaglebone White, Beaglebone Black and AM335x GP EVM Reported-by: Matt Ranostay <mranostay@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
| * | dts: peach_pi: Add DT properties needed for displayAjay Kumar2015-04-06-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add backlight enable GPIO, and delay needed for panel powerup via FIMD DT node. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | dts: peach_pit: Add SLP and RST GPIO properties in parade DT nodeAjay Kumar2015-04-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that parade driver supports reading SLP and RST GPIO from DT, specify the same in parade DT node. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | dts: exynos54xx: Add samsung, pwm-out-gpio property to FIMD nodeAjay Kumar2015-04-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the exynos_fb driver supports handling backlight GPIO via DT, specify pwm output property via FIMD DT node. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panelsAjay Kumar2015-04-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing setting for rpll_sdiv generates 70.5Mhz RPLL video clock to drive 1366x768 panel on peach_pit. This clock rate is not sufficient to drive 1920x1080 panel on peach-pi. So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock which can drive peach-pi LCD. This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD divider at IP level will get set to 1(the required divider setting will be calculated and set by exynos_fimd_set_clock()) and hence peach-pit LCD still works fine. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | arm: exynos: add display clocks for Exynos5800Ajay Kumar2015-04-06-3/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by exynos video driver. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos: Clock: Fix exynos5_get_periph_rate for I2C.Guillaume GARDET2015-04-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 2e82e9252695a612ab0cbf40fa0c7368515f6506 'Exynos: Clock: Cleanup soc_get_periph_rate' introduced a bug in I2C config. This patch makes cros_ec keyboard working again on Samsung Chromebook (snow). Changes in V2: reorder lines as requested by Joonyoung Shim. Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Joonyoung Shim <jy0922.shim@samsung.com> Reviewed-by: Simon Glass <sjg@chroimum.org> Tested-by: Simon Glass <sjg@chroimum.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-04-03-22/+128
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/armltd/vexpress64/vexpress64.c Signed-off-by: Tom Rini <trini@konsulko.com>
| | * | tegra: pinmux: fix FUNCMUX_NDFLASH_KBC_8_BITLucas Stach2015-03-30-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even the 8-bit case needs KBCB configured, as pin D7 is located in this pingroup. Please note that pingroup ATC seems to come out of reset with its config set to NAND so one needs to explicitly configure some other function to this group in order to avoid clashing settings which is outside the scope of this patch. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | ARM: tegra: fix colibri_t20 machine typeMarcel Ziswiler2015-03-30-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A while ago I got Russell to change the machine type of our Colibri T20 from COLIBRI_TEGRA2 to COLIBRI_T20 which at least in parts is also reflected in his machine registry: http://www.arm.linux.org.uk/developer/machines/list.php?id=3323 For us it is really very beneficial to actually still be able to boot downstream L4T kernel with its working hardware accelerated graphics/multimedia stack albeit it being proprietary/closed-source. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | ARM: tegra: rename colibri_t20 board/configuration/device-treeMarcel Ziswiler2015-03-30-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In accordance with our other modules supported by U-Boot and as agreed upon for Apalis/Colibri T30 get rid of the carrier board in the board/ configuration/device-tree naming. While at it also bring the prompt more in line with our other products. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | ARM: tegra: enable MIPI PAD CTRL support for Tegra124Stephen Warren2015-03-30-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows selection between CSI and DSI_B on the MIPI pads. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | ARM: tegra: pinctrl: add support for MIPI PAD control groupsStephen Warren2015-03-30-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some pinmux controls are in a different register set. Add support for manipulating those in a similar way to existing pins/groups. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | ARM: tegra: pinctrl: minor cleanupStephen Warren2015-03-30-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move struct pmux_pingrp_desc type and tegra_soc_pingroups variable declaration together with other pin/mux level definitions. Now the whole file is grouped/ordered pin/mux-related then drvgrp-related definitions. Fix typo in ifdef comment. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | ARM: tegra: pinctrl: move Tegra210 code to the correct dirStephen Warren2015-03-30-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patches that added the Tegra210 pinctrl driver and renamed directories arch/arm/cpu/tegra{$soc}-common -> arch/arm/mach-tegra/tegra-${soc} crossed. Move the Tegra210 pinctrl driver to the correct location. This wasn't detected since Tegra210 support is in the process of being added, and isn't buildable yet. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-03-31-151/+142
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| | * | | ARM: atmel: at91sam9n12ek: enable spl supportBo Shen2015-04-01-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPL support for at91sam9n12ek boards, now it supports boot up from NAND flash, serial flash. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| | * | | ARM: atmel: at91sam9x5ek: enable spl supportBo Shen2015-04-01-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPL support for at91sam9x5ek board. Now, it supports boot up from NAND flash and SPI flash. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| | * | | ARM: atmel: at91sam9m10g45ek: enable spl supportBo Shen2015-04-01-1/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Supports boot up from NAND flash with software ECC eanbled. And supports boot up from SD/MMC card with FAT file system. As the boot from SD/MMC card with FAT file system, the BSS segment is too big to fit into SRAM, so, use the lds to put it into SDRAM. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| | * | | ARM: atmel: arm926ejs: fix clock configurationBo Shen2015-04-01-26/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Config MCKR according to the datasheet sequence, or else it will cause the MCKR configuration failed. Remove timeout checking for clock configuration, if configure the clock failed, let the system hang while not run in wrong clock configuration. Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Heiko Schocher <hs@denx.de>
| | * | | spl_atmel.c: Switch s_init to board_init_fTom Rini2015-04-01-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To facilitate changing lowlevel_init to become s_init, move the current contents of s_init into board_init_f and add the rest of what board_init_f does here. In order to compile clean without CONFIG_SKIP_LOWLEVEL_INIT set, leave an empty stub of s_init(). It can be removed when lowlevel_init becomes s_init. Cc: Bo Shen <voice.shen@atmel.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Matt Porter <mporter@konsulko.com> on sama5d3_xplained Signed-off-by: Tom Rini <trini@ti.com> [rebased on current master, leave s_init() as empty stub] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| | * | | ARM: atmel: armv7: switch to use common timer functionsBo Shen2015-04-01-61/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 8dfafdd (Introduce common timer functions), add common timer functions, we can use them directly. Signed-off-by: Bo Shen <voice.shen@atmel.com> [rebase on current master] Sigend-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| | * | | ARM: atmel: arm9: switch to use common timer functionsBo Shen2015-04-01-59/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com> [rebase on current master] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | | Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini2015-03-31-0/+52
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| | * | board/seco: Add mx6q-uq7 basic board supportBoris BREZILLON2015-03-23-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic SECO MX6Q/uQ7 board support (Ethernet, UART, SD are supported). It also adds a Kconfig skeleton to later add more SECO board (supporting SoC and board variants). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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