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| author | Ye.Li <B37916@freescale.com> | 2014-06-12 19:34:18 +0800 |
|---|---|---|
| committer | Peng Fan <Peng.Fan@freescale.com> | 2015-04-29 14:42:24 +0800 |
| commit | 01b88201aa86bef26a4254ac43aff90e99fd2c06 (patch) | |
| tree | b2ced2e8c84ec0c125880f89a1be5f0262fe9e95 /arch/arm | |
| parent | 903a59ef941f39b6d7f693dd7c60528e166de079 (diff) | |
| download | u-boot-imx-01b88201aa86bef26a4254ac43aff90e99fd2c06.zip u-boot-imx-01b88201aa86bef26a4254ac43aff90e99fd2c06.tar.gz u-boot-imx-01b88201aa86bef26a4254ac43aff90e99fd2c06.tar.bz2 | |
ENGR00315894-77 mx6 soc: Add vadc power up/down function
Add vadc power up/down function.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 96d990ef754a879f6ca9da4adf6e0be3d21cdc51)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
arch/arm/include/asm/arch-mx6/imx-regs.h
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 46 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 13 |
2 files changed, 59 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 0e7b457..00a31e4 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -305,6 +305,52 @@ static void init_src(void) writel(val, &src_regs->scr); } +#ifdef CONFIG_MX6SX +void vadc_power_up(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_GPR_BASE_ADDR; + u32 val; + + /* csi0 */ + val = readl(&iomux->gpr[5]); + val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK, + val |= IMX6SX_GPR5_CSI1_MUX_CTRL_CVD; + writel(val, &iomux->gpr[5]); + + /* Power on vadc analog + * Power down vadc ext power */ + val = readl(GPC_BASE_ADDR + 0); + val &= ~0x60000; + writel(val, GPC_BASE_ADDR + 0); + + /* software reset afe */ + val = readl(&iomux->gpr[1]); + writel(val | 0x80000, &iomux->gpr[1]); + + udelay(10*1000); + + /* Release reset bit */ + writel(val & ~0x80000, &iomux->gpr[1]); + + /* Power on vadc ext power */ + val = readl(GPC_BASE_ADDR + 0); + val |= 0x40000; + writel(val, GPC_BASE_ADDR + 0); +} + +void vadc_power_down(void) +{ + u32 val; + + /* Power down vadc ext power + * Power off vadc analog */ + val = readl(GPC_BASE_ADDR + 0); + val &= ~0x40000; + val |= 0x20000; + writel(val, GPC_BASE_ADDR + 0); +} +#endif + static void imx_set_vddpu_power_down(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 9b662a0..ecf4c30 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -535,6 +535,14 @@ struct gpc { #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) +#ifdef CONFIG_MX6SX +#define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK (0x3 << 4) +#define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN (0x0 << 4) +#define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD (0x1 << 4) +#define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI (0x2 << 4) +#define IMX6SX_GPR5_CSI1_MUX_CTRL_GND (0x3 << 4) +#endif + /* ECSPI registers */ struct cspi_regs { u32 rxdata; @@ -1100,5 +1108,10 @@ struct mxs_lcdif_regs { #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 +#ifdef CONFIG_MX6SX +extern void vadc_power_up(void); +extern void vadc_power_down(void); +#endif + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ |