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| * | rockchip: Add basic support for firefly-rk3288Simon Glass2015-09-02-0/+544
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Firefly RK3288 is a suitable target board for initial mainline Rockchip support. It includes a good set of peripherals, a recent SoC and it is readily available. This adds only some basic files required to allow the baord to display a serial message in SPL and hang. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Add SPI driverSimon Glass2015-09-02-0/+20
| | | | | | | | | | | | | | | | | | | | | Add a SPI driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Add I2C driverSimon Glass2015-09-02-0/+70
| | | | | | | | | | | | | | | | | | | | | Add an I2C driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Add core SoC start-up codeSimon Glass2015-09-02-0/+432
| | | | | | | | | | | | | | | | | | | | | Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: Add SDRAM initSimon Glass2015-09-02-0/+1455
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses device tree for configuration so should be able to support other RAM configurations. It may be possible to generalise the code to support other SoCs at some point. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: Add a simple syscon driverSimon Glass2015-09-02-0/+26
| | | | | | | | | | | | | | | | | | Add a driver that provides access to system controllers. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: Add SoC reset driverSimon Glass2015-09-02-0/+54
| | | | | | | | | | | | | | | | | | | | | We can reset the SoC using some CRU (clock/reset unit) registers. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: Add header files for PMU and GRFSimon Glass2015-09-02-0/+857
| | | | | | | | | | | | | | | | | | | | | PMU is the power management unit and GRF is the general register file. Both are heavily used in U-Boot. Add header files with register definitions. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: Add clock driverSimon Glass2015-09-02-0/+185
| | | | | | | | | | | | | | | | | | | | | Add a driver for setting up and modifying the various PLLs and peripheral clocks on the RK3288. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Add basic peripheral and clock definitionsSimon Glass2015-09-02-0/+119
| | | | | | | | | | | | | | | | | | | | | | | | Add header files for the peripherals and clocks supported on Rockchip platforms. The particular implementation (and register set) for each is SoC-specific, but it seems that the naming can be generic. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: gpio: Add rockchip GPIO driverSimon Glass2015-09-02-0/+28
| | | | | | | | | | | | | | | | | | | | | This supports RK3288 at present. It does not implement functions or support for pull up/down. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: dts: Make core devices available earlySimon Glass2015-09-02-0/+15
| | | | | | | | | | | | | | | | | | | | | In SPL we need access to the CRU and other peripherals so we can set up SDRAM. Mark these so that they will remain in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Bring in RK3288 device tree file includes and bindingsSimon Glass2015-09-02-0/+1546
| | | | | | | | | | | | | | | | | | | | | | | | Bring in required device tree files from Linux. Since mainline Linux is somewhat behind, use the files from the Chromium tree. We can re-sync once further code is acccepted upstream. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | arm: reset: Avoid a build error when the reset uclass is enabledSimon Glass2015-09-02-0/+2
| | | | | | | | | | | | | | | | | | | | | There can be only one do_reset(). When CONFIG_RESET is enabled this is provided by the reset uclass, and ARM's version should be disabled. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | arch/arm/Kconfig: Add back in missing entries.Tom Rini2015-09-02-0/+2
| | | | | | | | | | | | | | | | | | | | | In 2178282 we accidentally dropped out hilsilicon and cm_t43. Bring these back in. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | Convert omap3_logic to ti_omap3_common.hAdam Ford2015-09-02-0/+3
| | | | | | | | | | | | | | | | | | | | | Convert to using the common config files. Signed-off-by: Adam Ford <adam.ford@logicpd.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-09-02-277/+2228
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| * | | imx: vf610 add get_cpu_revPeng Fan2015-09-02-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we need to support runtime check for different drivers, we need to add get_cpu_rev for vf610, otherwise there will be build errors. This patch introduces a dummy CPU id which is not read from chip silicon. Later when we can get the real id from chip, can fix the value of MXC_CPU_VF610 then. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Suggested-by: Stefano Babic <sbabic@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | mxc: ocotp fix hole in shadow registersPeng Fan2015-09-02-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a hole in shadow registers address map of size 0x100 between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL. Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, we should account for this hole in address space. Similar hole exists between bank 14 and bank 15 of size 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. Note: iMX6SL has only 0-7 banks and there is no hole. Note: iMX6UL doesn't have this one. When reading, we use register offset, so need to account for holes to get the correct address. When writing, we use bank/word index, there is no need to account for holes, always use bank/word index from fuse map. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * | | arm, imx6: add aristainetos 2b board versionHeiko Schocher2015-09-02-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | there is a 2b board version of the aristainetos2 board. Differences to the v2: - spi cs for the nor flash and display controller changed - some pinmux changes - LED gpio settings changed Signed-off-by: Heiko Schocher <hs@denx.de>
| * | | imx: mx6ul_14x14_evk select MX6ULPeng Fan2015-09-02-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to expose SoC choice to user, we already got the SoC according to the build target. So default "select MX6UL" for MX6UL_14x14_EVK target. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * | | arm: Add SYS_L2CACHE_OFF Kconfig entryPeng Fan2015-09-02-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To i.MX6UL, SYS_L2CACHE_OFF is selected, but there is no Kconfig entry for SYS_L2CACHE_OFF. Then "select SYS_L2CACHE_OFF" does not effect for i.MX6UL, which is not expected. Since SYS_L2CACHE_OFF is mainly used by ARM architecture, add it to arch/arm/Kconfig. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | imx: mx6slevk: add SPL supportPeng Fan2015-09-02-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SPL boot support for mx6slevk board. 1. Introduce a configuration file mx6slevk_spl_defconfig. 2. i.MX6SL has same DRAM space with i.MX6SX, need to change SPL DRAM SPACE. 3. Include imx6_spl.h and related SPL macro in mx6slevk.h. 4. select SUPPORT_SPL for TARGET_MX6SLEVK. 5. Add SPL board code to do related initialization. Boot Log: U-Boot SPL 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59) reading u-boot.img reading u-boot.img U-Boot 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59 +0000) CPU: Freescale i.MX6SL rev1.2 996 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 50C Reset cause: POR Board: MX6SLEVK I2C: ready DRAM: 1 GiB PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * | | imx: mx6: ddr: add LPDDR2 supportPeng Fan2015-09-02-4/+311
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add LPDDR2 support: 1. Implement a function mx6_lpddr2_cfg to initialize MMDC for LPDDR2. 2. Introduce a structure mx6_lpddr2_cfg, most entrys are same to mx6_ddr3_cfg, but still keep it a single one for easy to choose parameters for LPDDR2. 3. If ddr_type is LPDDR2, use mx6_lpddr2_cfg to init MMDC. 4. Update comments. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | | imx: mx6: ddr init MMDC according to ddr_typePeng Fan2015-09-02-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper. The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg when ddr_type is for DDR3. Later we can use ddr_type to initialize MMDC for LPDDR2. Initialize ddr_type for different boards which enable SPL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Stefan Roese <sr@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | imx: mx6: ddr add an entry ddr_type for mx6_ddr_sysinfoPeng Fan2015-09-02-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ddr_type entry for mx6_ddr_sysinfo. It will be used for differenrate DDR3 and LPDDR2. Introduce an enum type for ddr_type. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | | imx: mx6: ddr add mpzqlp2ctl entryPeng Fan2015-09-02-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add mpzqlp2ctl entry for mx6_mmdc_calibration. MMDC_MPZQLP2CTL register is for init tZQINIT, tZQCL, tZQCS for LPDDR2 chips. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | | imx: mx6: ddr add dram io configuration and header file for i.MX6SLPeng Fan2015-09-02-0/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define two structure mx6sl_iomux_ddr_regs and mx6sl_iomux_grp_regs. Add a new function mx6sl_dram_iocfg to configure dram io. Add header file to define macros for register address. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | imx: mx6: ddr correct tRFC and tXSPeng Fan2015-09-02-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To Chip density 4Gb, tRFC should be 300ns, see "Table 61 — Refresh parameters by device density" of JESD79-3E. tXS(min) is max(5nCK, tRFC(min) + 10ns). Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | | imx: mx6: ddr no support MMDC1 for i.MX6SLPeng Fan2015-09-02-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX 6SoloLite only supports MMDC0, so do not access MMDC1 for i.MX 6SL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | | imx: mx6: ddr add more register entry for mmdc_p_regsPeng Fan2015-09-02-9/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add more register entry for MMDC structure. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | | tbs2910: use full name in Kconfig board selectionSoeren Moch2015-09-02-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Soeren Moch <smoch@web.de>
| * | | imx: mxc_gpio: add support for imx7d SoCAdrian Alonso2015-09-02-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add mxc_gpio support for imx7d SoC * Use CONFIG_MX7 to extend mxc gpio driver support for imx7d Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
| * | | imx: iomux-v3: add imx7d support for iomuxcAdrian Alonso2015-09-02-0/+1377
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add imx7d support for iomux controller * imx7d has two iomux controllers iomuxc (0x3033000) and iomuxc-lpsr (0x302C0000) each conroller provides control and mux mode pad registers but shares iomuxc input select register with iomuxc-lpsr IOMUX_CONFIG_LPSR flag is used to properly set daisy chain settings for iomuxc-lpsr pads. * Since mx7d introduces LPSR IOMUX pins, add new base to IOMUX v3 driver for these LPSR pins. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
| * | | imx: clock support enet2 anatop clock supportPeng Fan2015-09-02-6/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To i.MX6SX/UL, two ethernet interfaces are supported. Add ENET2 clock support: 1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed. To value 1, only i.MX6SX/UL can pass the check. 2. Modify board code who use this api to follow new api prototype. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | imx-common: consolidate macros and prototypes into sys_proto.hPeng Fan2015-09-02-87/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move most macro definitions and prototypes into "arch/arm/include/asm/imx-common/sys_proto.h" to avoid duplicated function prototypes and marco definitions for different i.MX SoCs. This patch do not remove the sys_proto.h for different i.MX SoCs, because we need to modify lots of driver code and others. This patch remove duplicated macros and prototypes and incude "sys_proto.h" of imx-common for each sys_proto.h of different i.MX platforms. Then later we should avoid add stuff in sys_proto.h of each platform, and modify driver to include common sys_proto.h. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | | imx: mxs: reimplement get_cpu_revPeng Fan2015-09-02-28/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rewrite get_cpu_rev, from "static const char *get_cpu_rev(void)" to "u32 get_cpu_rev(void)". To align with get_cpu_rev of other i.MXes. Also write get_imx_type to replace get_cpu_type, since we have macro named get_cpu_type. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | | imx: mx31 use new formula for get_cpu_revPeng Fan2015-09-02-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use new formula for get_cpu_rev, since we need to use this formula to do runtime check for all i.MXes. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | | imx: mx27 implement get_cpu_revPeng Fan2015-09-02-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement get_cpu_rev to support runtime check using is_cpu_type. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | | imx: add cpu type for i.MX2 and i.MX3Peng Fan2015-09-02-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add cpu types for i.MX2/3. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | | imx: mx6 move TARGET_xx Kconfig option to mx6 specific Kconfig filePeng Fan2015-09-02-132/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move TARGET_xx Kconfig option based on mx6 to arch/arm/cpu/armv7/mx6/Kconfig. Add enable "CONFIG_ARCH_MX6" for boards based on mx6. Then we can choose target boards using "make ARCH=arm menuconfig" with ARCH_MX6 defined. If using original way, we have no chance to enable ARCH_MX6 when "make menuconfig". Even define CONFIG_ARCH_MX6=y in xx_defconfig, kconfig will complains "arch/../configs/platinum_titanium_defconfig:3: warning: override: TARGET_PLATINUM_TITANIUM changes choice state" Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Eric Bénard <eric@eukrea.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Marek Vasut <marex@denx.de> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Soeren Moch <smoch@web.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Soeren Moch <smoch@web.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * | | ARM: ts4800: add ethernet supportDamien Riegel2015-09-02-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds ethernet support to the TS4800. Note that the MAC address is not fused on this board and have to be read from FEC PALR PAUR registers (this is how the kernel provided by Technologic Systems does it). signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | ARM: ts4800: add basic board supportLucile Quirion2015-09-02-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds basic support including: MMC, Serial console, TS4800 watchdog The config use CONFIG_SKIP_LOWLEVEL_INIT as U-boot is used as a second stage bootloader. Signed-off-by: Lucile Quirion <lucile.quirion@savoirfairelinux.com> signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | arm: mxs: Fix mkimage invocationMarek Vasut2015-09-02-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove this ad-hoc mkimage invocation in MXS Makefile and replace it with the standard mkimage rule instead. This patch fixes recent build issues introduced by the patch 92a655c mkimage: Set up a file size parameter and keep it updated These build issues could be triggered by building for example the MX28EVK and the u-boot.sb image: $ make mx28evk_defconfig $ make V=1 u-boot.sb [...] make -f ./scripts/Makefile.build obj=arch/arm/cpu/arm926ejs/mxs u-boot.sb ./tools/mkimage -n arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg -T mxsimage u-boot.sb ./tools/mkimage: Can't open (null): Bad address arch/arm/cpu/arm926ejs/mxs/Makefile:82: recipe for target 'u-boot.sb' failed make[1]: *** [u-boot.sb] Error 1 Makefile:989: recipe for target 'u-boot.sb' failed make: *** [u-boot.sb] Error 2 With this patch: ./tools/mkimage -n arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg -T mxsimage -d arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg u-boot.sb Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Juha Lumme <juha.lumme@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | udoo: Switch to SPL supportvpeter42015-09-02-0/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we need to build one U-boot image for each of the udoo variants: quad and dual-lite. By switching to SPL we can support all two variants with a single binary. Based on the SPL for wandboard. Tested with OpenELEC (Open Embedded Linux Entertainment Center) on both boards. Signed-off-by: Peter Vicman <peter.vicman@gmail.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Peter Vicman <peter.vicman@gmail.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | armv8: fsl-lsch3: Rewrite MMU translation table entriesAlison Wang2015-09-01-179/+392
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch rewrites MMU translation table entries. To start, all table entries are written as "invalid", then "device-ngnrnr" and "normal" are written to the entries to enable access to specific addresses. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* | | arm/ls102xa:add hwconfig setting to support disable unused devicesZhuoyu Zhang2015-09-01-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DEVDISRn registers provides a mechanism for gating clocks of IP blocks that are not used. Here we implement hwconfig option to allow users to disable unused peripherals on the board. For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts, User can enable CONFIG_FSL_DEVICE_DISABLE and set "devdis:esdhc,qdma,edma" in hwconfig, thus ESDHC controller & eDMA/qDMA will be clock gated to save more power. Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | ls102xa: etsec: Use proper settings for BE BDsClaudiu Manoil2015-09-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the DMACTRL[LE] hack with recommended settings for ETSECDMAMCR to get the same end effect - obtaining big-endian buffer descriptors and frame data for eTSEC. The reset / default value for ETSECDMAMCR is preserved, excepting the BD and FR bits which are cleared to enable the BE mode in accordance with the H/W specifications. Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA" Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Tested-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | armv8: fsl-lsch3: Initiaze 4 MACs per QSGMII in dpmac_infoPrabhakar Kushwaha2015-09-01-1/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Every QSGMII SerDes Protocol usage 4 MACs. So add/repeat QSGMII information for 4 MACs in dpmac_info strucuture. Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | armv8: ls2085a: Update serdes1_cfg_tbl for 0x33 & 0x35 protocolPrabhakar Kushwaha2015-09-01-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Update 0x33 and 0x35 serdes protocol as per updated SoC document in array serdes1_cfg_tbl. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-10-10 02:31:52 +0000