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* armv8: ls2080: Change env variable "fdt_high"Saksham Jain2016-03-29-0/+7
| | | | | | | | | | "fdt_high" env variable was set to 0xcfffffff for secure boot. Change it to 0xa0000000 for LS2080 to be consistent with non-secure boot targets. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-lsch3: Copy Bootscript and header from NOR to DDRSaksham Jain2016-03-29-3/+25
| | | | | | | | | | | | | To unify steps for secure boot for xip (eg. NOR) and non-xip memories (eg. NAND, SD), bootscipts and its header are copied to main memory. Validation and execution are performed from there. For other ARM Platforms (ls1043 and ls1020), to avoid disruption of existing users, this copy step is not used for NOR boot. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080: Add bootscript header addr for secure bootSaksham Jain2016-03-29-0/+4
| | | | | | | | | | | | | | | | | | During secure boot, Linux image along with other images are validated using bootscript. This bootscript also needs to be validated before it executes. This requires a header for bootscript. When secure boot is enabled, default bootcmd is changed to first validate bootscript using the header and then execute the script. For ls2080, NOR memory map is different from other ARM SoCs. So a new address on NOR is used for this bootscript header (0x583920000). The Bootscript address is mentioned in this header along with addresses of other images. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080rdb: ls2080qds: Add secure boot supportSaksham Jain2016-03-29-2/+7
| | | | | | | | | | Sec_init has been called at the beginning to initialize SEC Block (CAAM) which is used by secure boot validation later for both ls2080a qds and rdb. 64-bit address in ESBC Header has been enabled. Secure boot defconfigs are created for boards (NOR boot). Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-lsch3: Add new header for secure bootSaksham Jain2016-03-29-1/+6
| | | | | | | | | | | | | | For secure boot, a header is used to identify key table, signature and image address. A new header structure is added for lsch3. Currently key extension (IE) feature is not supported. Single key feature is not supported. Keys must be in table format. Hence, SRK (key table) must be present. Max key number has increase from 4 to 8. The 8th key is irrevocable. A new barker Code is used. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080: Add configs for SEC, SecMon, SRK and DCFGSaksham Jain2016-03-29-0/+20
| | | | | | | | | | | Add configs for various IPs used during secure boot. Add address and endianness for SEC and Security Monitor. SRK are fuses in SFP (fuses for public key's hash). These are stored in little endian format. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080: Add SFP Configs for LS2080Saksham Jain2016-03-29-0/+7
| | | | | | | | | In LS2080, SFP has version 3.4. It is in little endian. The base address is 0x01e80200. SFP is used in Secure Boot to read fuses. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Skip reconfigure QSPI clock when booting from QSPIQianyu Gong2016-03-28-1/+1
| | | | | | | | The qspi_cfg register is set by PBI when booting from QSPI. No need to changing it again. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: x86: Drop command-line code when CONFIG_CMDLINE is disabledSimon Glass2016-03-22-0/+3
| | | | | | | | Update the link script to drop this code when not needed. This is only done for two architectures at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-03-22-144/+93
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| * armv8/fsl-lsch2: fix sdhc clock frequency valueYangbo Lu2016-03-21-0/+4
| | | | | | | | | | | | | | | | | | The eSDHC could select to use platform clock or peripheral clock to generate SD clock. The default selection is platform clock. So, fix the clock frequency value that's calculated for eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Updating entries in Serdes TablePratiyush Srivastava2016-03-21-7/+7
| | | | | | | | | | | | | | | | | | | | | | The serdes protocol entries in Serdes table 1 for protocol 0x03, 0x33, 0x35 and in Serdes table 2 for protocols 0x45 and 0x47 are updated to reflect the entries in current Reference Manual. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Reported-by: Jose Rivera <german.rivera@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Add workaround for erratum A-009803Shengzhou Liu2016-03-21-0/+1
| | | | | | | | | | | | | | | | | | During initial DDR training, false parity errors may be detected. This patch adds workaround to fix the erratum. Tested on LS2085QDS and LS2080RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * pci/layerscape: add defines for LUTStuart Yoder2016-03-21-0/+4
| | | | | | | | | | | | | | | | | | | | The per-PCI controller LUT (Look-Up-Table) is a 32-entry table that maps PCI requester IDs (bus/dev/fun) to a stream ID. Add defines for the register offsets. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: update stream ID partitioning infoStuart Yoder2016-03-21-21/+34
| | | | | | | | | | | | | | | | | | Update comments around how stream IDs are partitioned. Stream IDs allocated to PCI are no longer divided up by controller, but are instead a contiguous range Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: remove obsolete stream ID partitioning supportStuart Yoder2016-03-21-113/+0
| | | | | | | | | | | | | | | | | | | | Remove stream ID partitioning support that has been made obsolete by upstream device tree bindings that specify how representing how PCI requester IDs are mapped to MSI specifiers and SMMU stream IDs. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: ls102xa: fdt: Update FSL_QSPI_COMPAT and FSL_DSPI_COMPATAlison Wang2016-03-21-2/+2
| | | | | | | | | | | | | | | | | | As the compatible property values for QSPI and DSPI dts nodes are changed in kernel, FSL_QSPI_COMPAT and FSL_DSPI_COMPAT need to be updated too. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080ardb: invert irq pins polarity for AQR405 PHYShaohui Xie2016-03-21-0/+4
| | | | | | | | | | | | | | | | | | To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins polarity by setting IRQCR register, because AQR405 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: lsch3: Enable WUO config for RNI-20 nodePrabhakar Kushwaha2016-03-21-0/+31
| | | | | | | | | | | | | | | | | | | | Enable wuo config to accelerate coherent ordered writes for LS2080A and LS2085A. WRIOP IP is connected to RNI-20 Node. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm64: Fix layerscape mmu setupAlexander Graf2016-03-21-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm: socfpga: sr1500: Misc updates (SPI speed, env location)Stefan Roese2016-03-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes the following changes to the SR1500 board port: - Update defconfig to support SPI NOR (use make savedefconfig). - Increase SPI speed to a maximum of 100MHz for faster system bootup. - Change environment location, so that its not between SPL and main U-Boot. This way the combined SPL / U-Boot image can be used for updates. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de>
* | dts:exynos:update pinctrl size-cells and fix child regsPrzemyslaw Marczak2016-03-17-29/+29
|/ | | | | | | | | | | | | | | | | | | This change is required to avoid warnings about invalid size-cells defined in device-tree pinctrl nodes for Exynos. Tested on: - Odroid U3 - Odroid XU3 Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: Add a 64-bit division routine to the private librarySimon Glass2016-03-17-1/+247
| | | | | | | | | | | | This is missing, with causes lldiv() to fail on boards with use the private libgcc. Add the missing routine. Code is available for using the CLZ instruction but it is not enabled at present. This comes from coreboot version 4.0. Signed-off-by: Simon Glass <sjg@chromium.org>
* spl: arm: Make sure to include all of the u_boot_list entriesTom Rini2016-03-16-15/+9
| | | | | | | | | | | | | | Starting with 96e5b03 we use a linker list for partition table information. However since we use this in SPL we need to make sure that the SPL linker scripts include these as well. While doing this, it's best to simply include all linker lists to future proof ourselves. Cc: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reported-by: Nishanth Menon <nm@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XXTom Rini2016-03-16-1/+7
| | | | | | | | | | On OMAP4 platforms that also need to calculate their DDR settings we are now getting very close to the linker limit size. Since OMAP44XX is only seen with LPDDR2, remove some run time tests for LPDDR2 or DDR3 as we will know that we don't have it for OMAP44XX. Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: Only link cmd_ddr3.o on non-SPL buildsTom Rini2016-03-16-1/+2
| | | | | | | | | | | | When we switch to including all linker lists in SPL it is important to not include commands as that may lead to link errors due to other things we have already discarded. In this case simply move cmd_ddr3.o over to the list with the rest. Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: Switch to using the poweroff commandTom Rini2016-03-16-29/+30
| | | | | | | | | | Now that we have a standard way to power off the hardware, switch to using that rather than our own command. Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: Split monitor code / command codeTom Rini2016-03-16-52/+71
| | | | | | | | | | | | When we switch to including all linker lists in SPL it is important to not include commands as that may lead to link errors due to other things we have already discarded. In this case, we split the code for supporting the monitor out from the code for loading it. Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: DDR: Enable SR in Power Management ControlNishanth Menon2016-03-15-3/+3
| | | | | | | | | | | | | | If EMIF is idle for certain amount of DDR cycles, EMIF will put the DDR in self refresh mode to save power if EMIF_PWR_MGMT_CTRL register is programmed. And also before entering suspend-resume ddr needs to be put in self-refresh. Linux kernel does not program this register before entering suspend and relies on u-boot setting. So configuring it in u-boot. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: Allow EFI payload code to take exceptionsAlexander Graf2016-03-15-0/+8
| | | | | | | | | | | | | | | There are 2 ways an EFI payload could return into u-boot: - Callback function - Exception While in EFI payload mode, r9 is owned by the payload and may not contain a valid pointer to gd, so we need to fix it up. We do that properly for the payload to callback path already. This patch also adds gd pointer restoral for the exception path. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Allow EFI payload code to take exceptionsAlexander Graf2016-03-15-0/+9
| | | | | | | | | | | | | | | There are 2 ways an EFI payload could return into u-boot: - Callback function - Exception While in EFI payload mode, x18 is owned by the payload and may not contain a valid pointer to gd, so we need to fix it up. We do that properly for the payload to callback path already. This patch also adds gd pointer restoral for the exception path. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Allow exceptions to returnAlexander Graf2016-03-15-0/+34
| | | | | | | | | | | | | | Our current arm64 exception handlers all panic and never return to the exception triggering code. But if any handler wanted to continue execution after fixups, it would need help from the exception handling code to restore all registers. This patch implements that help. With this code, exception handlers on aarch64 can successfully return to the place the exception happened (or somewhere else if they modify elr). Signed-off-by: Alexander Graf <agraf@suse.de>
* efi_loader: Add runtime servicesAlexander Graf2016-03-15-0/+54
| | | | | | | | | | | | | | | | | After booting has finished, EFI allows firmware to still interact with the OS using the "runtime services". These callbacks live in a separate address space, since they are available long after U-Boot has been overwritten by the OS. This patch adds enough framework for arbitrary code inside of U-Boot to become a runtime service with the right section attributes set. For now, we don't make use of it yet though. We could maybe in the future map U-boot environment variables to EFI variables here. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* arm64: Only allow dcache disabled in SPL buildsAlexander Graf2016-03-15-0/+9
| | | | | | | | | Now that we have an easy way to describe memory regions and enable the MMU, there really shouldn't be anything holding people back from running with caches enabled on AArch64. To make sure people catch early if they're missing on the caching fun, give them a compile error. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Remove non-full-va map codeAlexander Graf2016-03-15-216/+85
| | | | | | | | | | | By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de>
* tegra: Replace home grown mmu code with generic table approachAlexander Graf2016-03-15-115/+17
| | | | | | | Now that we have nice table driven page table creating code that gives us everything we need, move to that. Signed-off-by: Alexander Graf <agraf@suse.de>
* zymqmp: Replace home grown mmu code with generic table approachAlexander Graf2016-03-15-169/+48
| | | | | | | Now that we have nice table driven page table creating code that gives us everything we need, move to that. Signed-off-by: Alexander Graf <agraf@suse.de>
* thunderx: Move mmu table into board fileAlexander Graf2016-03-15-5/+5
| | | | | | | | | The MMU range table can vary depending on things we may only find out at runtime. While the very simple ThunderX variant does not change, other boards will, so move the definition from a static entry in a header file to the board file. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Make full va map code more dynamicAlexander Graf2016-03-15-100/+494
| | | | | | | | | | | | | | | | | | | The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Disable TTBR1 maps in EL1Alexander Graf2016-03-15-1/+2
| | | | | | | | | | | | When running in EL1, AArch64 knows two page table maps. One with addresses that start with all zeros (TTBR0) and one with addresses that start with all ones (TTBR1). In U-Boot we don't care about the high up maps, so just disable them to ensure we don't walk an invalid page table by accident. Reported-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* thunderx: Calculate TCR dynamicallyAlexander Graf2016-03-15-6/+59
| | | | | | | | Based on the memory map we can determine a lot of hard coded fields of TCR, like the maximum VA and max PA we want to support. Calculate those dynamically to reduce the chance for pit falls. Signed-off-by: Alexander Graf <agraf@suse.de>
* omap4: Check warm reset for reboot mode validityPaul Kocialkowski2016-03-15-0/+4
| | | | | | | Since the SAR registers are filled with garbage on cold reset, this checks for a warm reset to assert the validity of reboot mode. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Reboot mode supportPaul Kocialkowski2016-03-15-0/+49
| | | | | | | | | | Reboot mode is written to SAR memory before reboot in the form of a string. This mechanism is supported on OMAP4 by various TI kernels. It is up to each board to make use of this mechanism or not. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Properly enable USB PHY clocksPaul Kocialkowski2016-03-15-1/+9
| | | | | | | This correctly enables the USB PHY clocks, by enabling CM_ALWON_USBPHY_CLKCTRL and correctly setting CM_L3INIT_USBPHY_CLKCTRL's value. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap-common: clocks-common: Setup USB DPLL when MUSB is in usePaul Kocialkowski2016-03-15-2/+4
| | | | | | | | On (at least) OMAP4, the USB DPLL is required to be setup for the internal PHY to work properly. The internal PHY is used by default with the MUSB USB OTG controller. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* Amazon Kindle Fire (first generation) codename kc1 supportPaul Kocialkowski2016-03-15-0/+4
| | | | | | | | | | The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was released by Amazon back in 2011. It is using an OMAP4430 SoC GP version, which allows running U-Boot and the U-Boot SPL from the ground up. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Move i2c clocks enable to enable_basic_clocksPaul Kocialkowski2016-03-15-4/+4
| | | | | | | I2C is often enabled withing the U-Boot SPL, thus those clocks are required to be enabled early (especially when the bootrom doesn't enable them for us). Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Remove duplicate CM_L3INIT_USBPHY_CLKCTRL reference and whitespacePaul Kocialkowski2016-03-15-2/+1
| | | | | | | This removes a duplicate reference to CM_L3INIT_USBPHY_CLKCTRLin enable_basic_uboot_clocks. Also, a doubled whitespace is removed. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap-common: Remove deprecated arch_cpu_init codePaul Kocialkowski2016-03-15-13/+0
| | | | | | | save_omap_boot_params is called from spl_board_init in the SPL context. Thus, there is no reason to duplicate that call on arch_cpu_init. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap-common: Rename set_muxconf_regs_essential to set_muxconf_regsPaul Kocialkowski2016-03-15-4/+4
| | | | | | | There is no distinction between essential and non-essential mux configuration, so it doesn't make sense to have an "essential" prefix. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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