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| author | Alexander Graf <agraf@suse.de> | 2016-03-04 01:09:46 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-03-15 15:13:00 -0400 |
| commit | 9bb367a590feac21d674e4d2cee77702d4774819 (patch) | |
| tree | 03ded1f537f9b0c2857f6efe1de441635206466b /arch/arm | |
| parent | 0691484ac1efb1981dfd1b38df9646128bafff32 (diff) | |
| download | u-boot-imx-9bb367a590feac21d674e4d2cee77702d4774819.zip u-boot-imx-9bb367a590feac21d674e4d2cee77702d4774819.tar.gz u-boot-imx-9bb367a590feac21d674e4d2cee77702d4774819.tar.bz2 | |
arm64: Disable TTBR1 maps in EL1
When running in EL1, AArch64 knows two page table maps. One with addresses
that start with all zeros (TTBR0) and one with addresses that start with all
ones (TTBR1).
In U-Boot we don't care about the high up maps, so just disable them to ensure
we don't walk an invalid page table by accident.
Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv8/cache_v8.c | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/armv8/mmu.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 9229532..d92f2d1 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -71,7 +71,7 @@ static u64 get_tcr(int el, u64 *pips, u64 *pva_bits) } if (el == 1) { - tcr = TCR_EL1_RSVD | (ips << 32); + tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE; } else if (el == 2) { tcr = TCR_EL2_RSVD | (ips << 16); } else { diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 39ff745..0080ae6 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -154,6 +154,7 @@ #define TCR_TG0_4K (0 << 14) #define TCR_TG0_64K (1 << 14) #define TCR_TG0_16K (2 << 14) +#define TCR_EPD1_DISABLE (1 << 23) #ifndef CONFIG_SYS_FULL_VA #define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */ |