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* rockchip: rk3036: Add core Soc start-up codehuang lin2015-12-01-2/+104
| | | | | | | | | | | | | | | | rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
* rockchip: add rk3036 sdram driverhuang lin2015-12-01-0/+1107
| | | | | | | add rk3036 sdram driver so we can set up sdram in SPL Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: add early uart driverhuang lin2015-12-01-0/+108
| | | | | | | | add early uart driver so we can print debug message in SPL stage Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: mmc: get the fifo mode and fifo depth property from dtshuang lin2015-12-01-0/+1
| | | | | | | | rk3036 mmc do not have internal dma, so we use fifo mode when read and write data, we get the fifo mode and fifo depth property from dts, pass to dw_mmc driver. Signed-off-by: Lin Huang <hl@rock-chips.com>
* rockchip: rk3036: Add a simple syscon driverhuang lin2015-12-01-1/+22
| | | | | | | Add a driver that provides access to system controllers Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: Add Soc reset driverhuang lin2015-12-01-0/+55
| | | | | | | | We can reset the Soc using some CRU (clock/reset unit) register. Add support for this. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: Add header files for GRFhuang lin2015-12-01-0/+493
| | | | | | | GRF is the gereral register file. Add header files with register definitions. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: Add clock driverhuang lin2015-12-01-0/+168
| | | | | | | | Add a driver for setting up and modifying the various PLLs, peripheral clocks and mmc clocks on RK3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Bring in RK3036 device tree file includes and bindingshuang lin2015-12-01-0/+427
| | | | | | | | | Since rk3036 device tree file still in reviewing, bring it from https://patchwork.kernel.org/patch/7203371/ and add some aliases we need in uboot Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: add config decide whether to build common.chuang lin2015-12-01-1/+1
| | | | | | | | some rockchips soc will not use uclass in SPL stage, so define config to decide whether to build common.c Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rename board-spl.c to rk3288-board-spl.chuang lin2015-12-01-1/+1
| | | | | | | | since different rockchip soc need different spl file, so rename board-spl.c. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfighuang lin2015-12-01-3/+3
| | | | | | | | | since different rockchip SOC have different size of SRAM, So the size SYS_MALLOC_F_LEN may different, so move this config to rk3288 own Kconfig Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: add timer driverhuang lin2015-12-01-19/+73
| | | | | | | | some rockchip soc will not include lib/timer.c in SPL stage, so implement timer driver for some soc can use us delay function in SPL. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Disable PCI compatibility functions by defaultSimon Glass2015-12-01-0/+1
| | | | | | | | | We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: tegra: pci: Convert tegra boards to driver model for PCISimon Glass2015-12-01-0/+5
| | | | | | | | | Adjust the Tegra PCI driver to support driver model and move all boards over at the same time. This can make use of some generic driver model code, such as the range-decoding logic. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: refactor common Kconfig optionsStephen Warren2015-12-01-18/+20
| | | | | | | | | | | This makes it easier to select common options in a single place, rather than having to add them separately for different SoCs or architectures. The lists of select statements are now also sorted for easy searching. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-11-30-63/+406
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| * arm: at91/spl: atmel_sfr: move saic redirect to separate fileWenyou Yang2015-11-30-15/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | To make saic redirect code sharing with other SoCs, move the saic redirect code from SAMA5D4 particular file, mach-at91/armv7/sama5d4_devices.c to a separate file, mach-at91/atmel_sfr.c Move ATMEL_SFR_AICREDIR_KEY definition to sama5d4.h, because each SoC has its own value. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: at91/spl: matrix: use matrix slave id macrosWenyou Yang2015-11-30-9/+34
| | | | | | | | | | | | | | | | To make matrix initialization code sharing with others, use the matrix slave id macros, instead of hard-coding. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: at91/spl: matrix: remove security peripheral select codeWenyou Yang2015-11-30-9/+0
| | | | | | | | | | | | | | | | | | Remove the security peripheral select code, keep the default value in these registers, that is, the peripheral address space is configured as "Secured" access, it is suitable for SPL. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: at91/spl: matrix: remove matrix write protection codeWenyou Yang2015-11-30-8/+0
| | | | | | | | | | | | | | | | | | On processor reset, the matrix write protection is disabled, so no need to disable/enable write protection when writing the matrix registers. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: at91/spl: matrix: move matrix init to separate fileWenyou Yang2015-11-30-43/+52
| | | | | | | | | | | | | | | | | | | | To make the matrix initialization code sharing with other SoCs, move it from SAMA5D4 particular file, mach-at91/armv7/sama5d4_devices.c to a separate file, mach-at91/matrix.c Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: atmel: Add SAMA5D2 Xplained boardWenyou Yang2015-11-30-6/+274
| | | | | | | | | | | | | | | | | | | | | | | | The board supports following features: - Boot media support: SD card/e.MMC/SPI flash, - Support LCD display (optional, disabled by default), - Support ethernet, - Support USB mass storage. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> [fix checkpatch warnings] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * gpio: atmel: Add the PIO4 driver supportWenyou Yang2015-11-30-0/+48
| | | | | | | | | | | | | | The PIO4 is introduced from SAMA5D2, as a new version for Atmel PIO controller. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-11-30-88/+783
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| * | armv8: fsl-layerscape: Fix early MMU table for nand bootYork Sun2015-11-30-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The early MMU table doesn't enable all addresses. Unused addresses are marked as invalid, as introduced by commit 9979922. An entry was missing for NAND flash space, causing nand boot failure. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com>
| * | armv8: ls2085a: Add workaround of errata A009635Prabhakar Kushwaha2015-11-30-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8: fsl-layerscape: Fix "cpu release" commandYork Sun2015-11-30-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | When one core is released, other cores may not have valid entry address. Those cores are trapped by "wfe" and wait for further instruction. When their address is set, they need to be kicked off by "sev". Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/layerscape: Update MMU table with execute-never bitsAlison Wang2015-11-30-31/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com>
| * | drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3York Sun2015-11-30-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Freescale LSCH3 platforms use two DDR controlers interleaving mode out of reset. It can be configured to disable one controller. To support this operation, the driver needs to detect and skip the disabled controller. Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043ardb: add USB supportGong Qianyu2015-11-30-3/+3
| | | | | | | | | | | | | | | | | | | | | Add support for the third USB controller for LS1043A. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043ardb: add DSPI supportGong Qianyu2015-11-30-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | Use the U-Boot Driver Model. Just enable Freescale DSPI driver and set DSPI related parameters in dts file. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043aqds: dts: add dtb supportGong Qianyu2015-11-30-1/+126
| | | | | | | | | | | | | | | | | | | | | Reuse the dts files from ls1043a linux kernel. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043aqds: add LS1043AQDS board supportShaohui Xie2015-11-30-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043AQDS Specification: ------------------------- Memory subsystem: * 2GByte DDR4 DIMM * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two RGMII ports * XFI 10G port * SGMII * QSGMII with 4x 1G ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> [York Sun: Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043ardb: dts: add dtb supportGong Qianyu2015-11-30-0/+245
| | | | | | | | | | | | | | | | | | | | | | | | Reuse dts files from ls1043a linux kernel. Some parts in dts files may not be needed by U-Boot. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/fsl-layerscape: Remove reference to gdataGong Qianyu2015-11-30-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The global_data pointer (gd) has been set earlier in crt0_64.S. So there's no need to assign it again. Remove gdata since it is going away in U-Boot. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | pci/layerscape: add support for LS1043A PCIe LUT register accessMingkai Hu2015-11-30-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8: ls2085a: Add support of LS2085A SoCPrabhakar Kushwaha2015-11-30-8/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's LS2085A is a another personality of LS2080A SoC with support of AIOP and DP-DDR. This Patch adds support of LS2085A Personality. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Updated MAINTAINERS files Dropped #ifdef in cpu.h Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha2015-11-30-48/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver: net: fsl-mc: Add DPAA2 commands to manage MCPrabhakar Kushwaha2015-11-30-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Management complex Firmware, DPL and DPC are depolyed during u-boot boot sequence. Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop and apply DPL from u-boot command prompt. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8: lsch3: Fix lane protocol parsing logicPrabhakar Kushwaha2015-11-30-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current implementation only consider SGMIIs for dpmac initialization. XFI serdes protocols also uses dpmac. Also, fix lane protocol parsing logic to consider both XFIs and SGMIIs. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls1021a: Ensure Generic Timer disabled before jumping into the OSAlison Wang2015-11-30-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch addresses a problem mentioned recently on this mailing list: [1]. In that posting a LS1021 based system was locking up at about 5 minutes after boot,but the problem was mysteriously related to the toolchain used for building u-boot.Debugging the problem reveals a stuck interrupt 29 on the GIC. It appears Freescale's LS1021 support in u-boot erroneously sets the 64-bit ARM generic PL1 physical time CompareValue register to all-ones with a 32-bit value.This causes the timer compare to fire 344 seconds after u-boot configures it.Depending on how fast u-boot gets the kernel booted,this amounts to about 5-minutes of Linux uptime before locking up. Apparently the bug is masked by some toolchains. Perhaps this is explained by default compiler options, word sizes, or binutils versions. To fix the above issue, the generic physical timer is disabled before jumping to the OS. [1] https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html Signed-off-by: Chris Kilgour <techie@whiterocker.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls1021a: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bitAlison Wang2015-11-30-2/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch addresses a problem mentioned recently on this mailing list: [1]. In that posting a LS1021 based system was locking up at about 5 minutes after boot, but the problem was mysteriously related to the toolchain used for building u-boot. Debugging the problem reveals a stuck interrupt 29 on the GIC. It appears Freescale's LS1021 support in u-boot erroneously sets the 64-bit ARM generic PL1 physical time CompareValue register to all-ones with a 32-bit value. This causes the timer compare to fire 344 seconds after u-boot configures it. Depending on how fast u-boot gets the kernel booted, this amounts to about 5-minutes of Linux uptime before locking up. Apparently the bug is masked by some toolchains. Perhaps this is explained by default compiler options, word sizes, or binutils versions. At any rate this patch makes the manipulation explicitly 64-bit which alleviates the issue. [1] https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html Signed-off-by: Chris Kilgour <techie@whiterocker.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-11-30-0/+62
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| * | arm: socfpga: dts: Adding drvsel and smplsel to dtsChin Liang See2015-11-30-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding new node drvsel and smplsel for SDMMC Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Jaehoon Chung <jh80.chung@samsung.com>
| * | arm: socfpga: Repair SoCrates boardMarek Vasut2015-11-30-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board was constantly parasiting on the CV SoCDK, so split it into it's own separate directory. Moreover, the board config was missing important bits, like simple-bus support in SPL, the DRAM configuration was incorrect and the DTS was also missing the pre reloc bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Jan Viktorin <viktorin@rehivetech.com>
| * | ARM: socfpga: rename the cyclone5 and arria5 base address fileDinh Nguyen2015-11-30-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | When adding support for the Arria10 platform, we're going to name the file base_addr_a10.h, so to be systematic about it, rename the socfpga_base_addr.h to be base_addr_ac5.h for the Arria5 and Cyclone5 platform. Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | ARM: socfpga: arria10: add base address map for Arria10Dinh Nguyen2015-11-30-0/+45
| | | | | | | | | | | | | | | | | | | | | Add the base address map for Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: reset: FIX address of tstscratch registerPhilipp Rosenberger2015-11-30-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | The Cyclone V Hard Processor System Technical Reference Manual in the chapter about the Reset Manager Module Address Map stats that the offset of the tstscratch register ist 0x54 not 0x24. Cyclone V Hard Processor System Technical Reference Manual cv_5v4 2015.11.02 page 3-17 Reset Manager Module Address Map Signed-off-by: Philipp Rosenberger <ilu@linutronix.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2015-11-30-2/+2
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