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| author | York Sun <yorksun@freescale.com> | 2015-11-04 09:53:10 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-11-30 09:11:11 -0800 |
| commit | 61bd2f75f5eaf645e2c90fe2294cba37f7d8627f (patch) | |
| tree | 1915b86c9f0ac16bb7bcc867f9412530de4588eb /arch/arm | |
| parent | 7023100971c96b043b0aee669c45d1fcb3e8557b (diff) | |
| download | u-boot-imx-61bd2f75f5eaf645e2c90fe2294cba37f7d8627f.zip u-boot-imx-61bd2f75f5eaf645e2c90fe2294cba37f7d8627f.tar.gz u-boot-imx-61bd2f75f5eaf645e2c90fe2294cba37f7d8627f.tar.bz2 | |
drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 5ce916c..afc329a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -67,6 +67,13 @@ #define CCI_MN_DVM_DOMAIN_CTL 0x200 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 +#define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) +#define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) +#define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ +#define CCN_HN_F_SAM_NODEID_MASK 0x7f +#define CCN_HN_F_SAM_NODEID_DDR0 0x4 +#define CCN_HN_F_SAM_NODEID_DDR1 0xe + #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) |