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* arm/dts/ls2085a: Bring in ls2085a dts files from linux kernelHaikun Wang2015-07-20-0/+120
| | | | | | | | Bring in required device tree files for ls2085a from Linux. These are initially unchanged and have a number of pieces not needed by U-Boot. Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm/ls102xa: Add little-endian mode support for audio IPsAlison Wang2015-07-20-1/+2
| | | | | | | | As SCFG_ENDIANCR register is added to choose little-endian or big-endian for audio IPs on Rev2.0 silion, little-endian mode is selected. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm/ls102xa: Add PSCI support for ls102xaWang Dongsheng2015-07-20-0/+130
| | | | | | | | | | | | Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform. Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.SWang Dongsheng2015-07-20-40/+54
| | | | | | | | | | timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls1021a: Remove the inappropriate use of the function 'sprintf'Alison Wang2015-07-20-10/+11
| | | | | | | | | | | As the function 'sprintf' does not check buffer boundaries but outputs to the buffer 'enet' of fixed size (16), this patch removes the function 'sprintf', and uses 'strcpy' instead. It will assign the character arrays 'enet' and 'phy' the corresponding character strings. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: device tree fixups for PCI stream IDsStuart Yoder2015-07-20-0/+120
| | | | | | | | | | | This patch adds the infrastructure to update device tree nodes to convey SMMU stream IDs in the device tree. Fixups are implemented for PCI controllers initially. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: partition stream IDsStuart Yoder2015-07-20-0/+64
| | | | | | | | | | | | Stream IDs on ls2085a devices are not hardwired and are programmed by sw. There are a limited number of stream IDs available, and the partitioning of them is scenario dependent. This header defines the partitioning between legacy, PCI, and DPAA2 devices. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm/errata: Update required bits for A57 cores erratasBhupesh Sharma2015-07-20-4/+4
| | | | | | | | | | This patch updates the setting of required bits for A57 cores erratas - 828024 and 826974 Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Dai Haruki <dai.haruki at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls2085a: Update SoC README for DDR layoutPrabhakar Kushwaha2015-07-20-0/+25
| | | | | | | | | | Update SoC README to provide details of - Memory regions - Memory used by MC and Debug server Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/fsl-ch3: Add support to print SoC personalityPrabhakar Kushwaha2015-07-20-0/+57
| | | | | | | | | | | This patch adds support to print out the SoC personality. Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: Fix DDR speed messageYork Sun2015-07-20-2/+2
| | | | | | | DDR speed should be in MT/s, not MHz. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
* armv8/ls2085a: call ft_pcie_setup() to change dts statusPrabhakar Kushwaha2015-07-20-0/+4
| | | | | | | | | call ft_pci_setup() to disable PCIe dts node if corresponding PCIe controller is disabled according to RCW Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-07-14-1/+68
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| * spi: cadence_qspi: add device tree binding docVikas Manocha2015-07-03-5/+0
| | | | | | | | | | | | | | | | This patch adds the device tree binding doc for the cadence qspi controller & also removes the not needed properties from the stv0991 device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| * spi: cadence_qspi: get sram size from device treeVikas Manocha2015-07-03-0/+2
| | | | | | | | | | | | | | | | | | sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| * stv0991: configure device tree for cadence qspi & flashVikas Manocha2015-07-03-0/+34
| | | | | | | | | | | | | | | | This patch add the device tree entry for qspi controller & spi flash memory. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| * stv0991: enable cadence qspi controller & spi flashVikas Manocha2015-07-03-0/+3
| | | | | | | | | | | | | | | | This patch does all the board configurations required to use the qspi controller & attached spi flash memory. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| * stv0991: configure clock & pad muxing for qspiVikas Manocha2015-07-03-1/+34
| | | | | | | | | | | | | | | | stv0991 has cadence qspi controller for flash interfacing, this patch configures the device pads & clock for the controller. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
* | usb: Add EHCI support for Armada 38x (mvebu)Stefan Roese2015-07-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | This patch adds USB EHCI host support for the common mvebu platform. Including the Armada 38x. Tested on DB-88F6280-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu: Add SATA/SCSI (AHCI) support for Armada A38xStefan Roese2015-07-10-0/+56
| | | | | | | | | | | | | | | | | | | | This patch adds support for the common AHCI controller on the Marvell Armada 38x. Tested on the Marvell DB-88F6820-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu: Add SDIO/SDHCI support for Armada A38xStefan Roese2015-07-10-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | Armada A38x implements an SDHCI compatible SDIO controller. This patch enables the Marvell driver to support this SoC. And enables the SDIO controller if selected by the board configuration. Tested on Marvell DB-88F6820-GP board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | sunxi: Adjust Ippo_q8h_v1_2_a33_1024x600 dts filename to match the upstream ↵Hans de Goede2015-07-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | kernel sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dts has been merged into the upstream Linux kernel as sun8i-a33-ippo-q8h-v1.2.dts, adjust u-boot to follow. Note we've never shipped a final u-boot version with the old name, so this is safe todo. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2015-07-07-25/+33
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| * | Revert "break build if it would produce broken binary"Simon Glass2015-07-07-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The root cause of this problem should now be fixed. This reverts commit a6a4c542d316b3401f0840ac5378743191bca851. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Tested-by: Pavel Machek <pavel@denx.de>
| * | arm: Add ENTRY/ENDPROC to private libgcc functionsSimon Glass2015-07-07-17/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_SYS_THUMB_BUILD is defined these functions may be called from Thumb code. Add the required ENTRY and ENDPROC bracketing so that BLX is used to call these ARM functions, instead of plain BL, which will fail. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Pavel Machek <pavel@denx.de>
| * | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-07-07-1437/+3038
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| * | | armv7: better comment in start.SPavel Machek2015-07-07-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix big/small letters in comment. Signed-off-by: Pavel Machek <pavel@denx.de> Tested-by: Marek Vasut <marex@denx.de>
* | | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-07-05-7/+161
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| * | | | sunxi: Add Sinlinx SinA33 defconfigChen-Yu Tsai2015-07-05-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sinlinx SinA33 is a core/daughter board SDK kit from Sinlinx. It has the A33 SoC, USB host, USB OTG, audio input/output, LCD, camera, SDIO and GPIO headers. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: Sync sun8i dts files with the linux kernelChen-Yu Tsai2015-07-05-0/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2. This adds a dts file for Sinlinx SinA33 dev board, and the required changes in the .dtsi files. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: Add support for UART0 in PB pin group on A33Chen-Yu Tsai2015-07-05-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A33 adds a pinmux function for UART0 in the PB pin group. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: rsb: Enable R_PIO clock before configuring external pinsChen-Yu Tsai2015-07-05-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original code was configuring the external pins after enabling the R_PIO clock, which meant the configuration never made it to the pin controller the first time in SPL. Why this was working before is uncertain. Maybe the state was left from a previous boot sequence, or RSB just happened to be the default configuration. However with some A33 chips, SPL failed to configure the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev board. Reordering the calls fixed this. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: hardware-feature-specific function index defines for PORT F UART0Chen-Yu Tsai2015-07-05-4/+4
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 487b327 ("sunxi: GPIO pin mux hardware-feature-specific function index defines") renamed all GPIO index defines, but missed the PORT F UART0 setup functions. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-07-03-10/+19
|\ \ \ \ | |/ / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: configs/tbs2910_defconfig configs/tqma6q_mba6_mmc_defconfig configs/tqma6q_mba6_spi_defconfig configs/tqma6s_mba6_mmc_defconfig configs/tqma6s_mba6_spi_defconfig include/configs/mx6_common.h Signed-off-by: Tom Rini <trini@konsulko.com>
| * | | imx: mx6 introuduce macro is_mx6dqpPeng Fan2015-06-27-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new revision CHIP_REV_2_0. Introudce macro is_mx6dqp, dqp means Dual/Quad Plus. Since Dual/Quad Plus use same cpu type with Dual/Quad, but different revision(Major Lower), we use this macro for Dual/Quad Plus. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | | imx: mx6 correct get_cpu_revPeng Fan2015-06-27-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DIGPROG register map: 23 ------- 16 | 15 ------ 8 | 7 --- 0 | Major upper | Major Lower | Minor | We also need to account for Major Lower. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | | imx: mx6 correct is_soc_rev usagePeng Fan2015-06-27-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | is_soc_rev should return a bool value, so use "==", but not "-", change (is_soc_rev(CHIP_REV_1_0) > 0) to (soc_rev() > CHIP_REV_1_0). This patch also add space between "&" for cpu_type(rev) macro. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | | arm: mx6: tqma6: CPU type selection via KconfigMarkus Niebel2015-06-27-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the first patch to remove the CONFIG_SYS_EXTRA_OPTIONS. This patch implements CPU type selection from Kconfig. Further Kconfig stuff is added later. Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
| * | | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-06-15-111/+137
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| * | | | patch - arm - define SYS_CACHELINE_SIZE for mx5Chris Kuethe2015-06-09-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too Signed-off-by: Chris Kuethe <chris.kuethe@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Matthew Starr <mstarr@hedonline.com> Cc: Andrej Rosano <andrej@inversepath.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Chris Kuethe <chris.kuethe@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | | | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-07-01-0/+35
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| * | | | | zynq: defconfig: Move CONFIG_OF_* to KconfigJagan Teki2015-07-01-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit moves: - CONFIG_OF_CONTROL - SPL_DISABLE_OF_CONTROL from zynq_*_defconfig files into arch/arm/Kconfig "config ARCH_ZYNQ" Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | | | dts: zynq: Enable spi1 for zc770_xm010 boardJagan Teki2015-07-01-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables spi1 for zynq zc770_xm010 board dts Signed-off-by: Jagan Teki <jteki@openedev.com> Tested-by: Jagan Teki <jteki@openedev.com>
| * | | | | spi: zynq_spi: Add fdt support in driverJagan Teki2015-07-01-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now zynq spi driver platform data is controlled by devicetree, enable the status by saying "okay" on respective board dts to use the devicetree generated platdata. Ex: &spi1 { status = "okay"; }; Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
| * | | | | dts: zynq: Add zynq spi controller nodesJagan Teki2015-07-01-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds zynq spi controller nodes in zynq-7000.dtsi. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
| * | | | | zynq: Kconfig: Enable dm spi and spi_flashJagan Teki2015-07-01-0/+2
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabled CONFIG_DM_SPI and CONFIG_DM_SPI_FLASH for zynq soc. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* | | | | ARM: UniPhier: add IDs for PH1-Pro5, ProXstream2, PH1-LD6bMasahiro Yamada2015-07-02-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This prepares for new SoCs support. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | | ARM: dts: UniPhier: re-license device tree files under GPLv2+/X11Masahiro Yamada2015-07-02-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current GPL only licensing on the device trees makes it very impractical for other software components licensed under another license. To make it easier to reuse them, the device trees for UniPhier SoCs and boards have already been dual-licensed in Linux. Follow this trend in U-boot too. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | | ARM: dts: UniPhier: sync device trees with the Linux kernelMasahiro Yamada2015-07-02-12/+178
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes code diff much easier. Device trees describe hardware attributes, which are independent of software architecture. It generally makes sense to synchronize them beyond software projects. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | dm: ls1021aqds: dts: Use "spi_dataflash" driver instead of "spi_flash_std" ↵Haikun Wang2015-06-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for DSPI flash The type of DSPI flash on ls1021aqds is AT45DB021, it has specail commands and page-size. Use the special spi flash driver instead of "spi_flash_std" driver. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Tested-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
generated by cgit v1.1 at 2024-11-10 15:30:56 +0000