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authorVikas Manocha <vikas.manocha@st.com>2015-07-02 18:29:42 -0700
committerJagan Teki <jteki@openedev.com>2015-07-03 13:50:53 +0530
commit51d558392bc71f9cfb58ce5ea70975dee6bf6292 (patch)
tree249bc20bf4b4c4bc82460f54ab0265e938517650 /arch/arm
parente67abcaacb8271a58c1a5e5afb17475bd8c3deaf (diff)
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stv0991: configure device tree for cadence qspi & flash
This patch add the device tree entry for qspi controller & spi flash memory. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/dts/stv0991.dts34
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts
index b25c48b..3b1efca 100644
--- a/arch/arm/dts/stv0991.dts
+++ b/arch/arm/dts/stv0991.dts
@@ -20,4 +20,38 @@
reg = <0x80406000 0x1000>;
clock = <2700000>;
};
+
+ aliases {
+ spi0 = "/spi@80203000"; /* QSPI */
+ };
+
+ qspi: spi@80203000 {
+ compatible = "cadence,qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x80203000 0x100>,
+ <0x40000000 0x1000000>;
+ clocks = <3750000>;
+ ext-decoder = <0>; /* external decoder */
+ num-cs = <4>;
+ fifo-depth = <256>;
+ bus-num = <0>;
+ status = "okay";
+
+ flash0: n25q32@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ reg = <0>; /* chip select */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ page-size = <256>;
+ block-size = <16>; /* 2^16, 64KB */
+ read-delay = <4>; /* delay value in read data capture register */
+ tshsl-ns = <50>;
+ tsd2d-ns = <50>;
+ tchsh-ns = <4>;
+ tslch-ns = <4>;
+ };
+ };
};