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* imx:mx6ul add clock supportPeng Fan2015-08-02-90/+159
| | | | | | | | | | | | | | | 1. Add enet, uart, i2c, ipg clock support for i.MX6UL. 2. Correct get_periph_clk, it should account for MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK. 3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function, but not use 'ifdef'. 4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX. 5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q) || defined....", only need one CONFIG_PCIE_IMX in header file. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx-common: timer: add i.MX6UL supportPeng Fan2015-08-02-3/+5
| | | | | | Add i.MX6UL GPT timer support. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6ULPeng Fan2015-08-02-0/+4
| | | | | | | Since i.MX6UL's cache line size is 64bytes, need to define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx: mx6ul: Update imx registers head filePeng Fan2015-08-02-25/+35
| | | | | | | | | | | | 1. Update imx register base address for i.MX6UL. 2. Remove duplicated MXS_APBH/GPMI/BCH_BASE. 3. Remove #ifdef for register addresses that equal to "AIPS2_OFF_BASE_ADDR + 0x34000" for different chips. 4. According fuse map, complete fuse_bank4_regs. 5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX, because we can use runtime check Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx: mx6ul: Add pins IOMUX head filePeng Fan2015-08-02-0/+1067
| | | | | | | Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* imx: mx6ul: Add i.MX6UL CPU typePeng Fan2015-08-02-1/+4
| | | | | | | | | | Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which is not real id from DIGPROG register, so change i.MX6D to value 0x67 which was not occupied. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* arm: mx6: kconfig: don't select CPU_V7 per boardNikita Kiryanov2015-08-02-3/+0
| | | | | | | | | | CPU_V7 is already selected by ARCH_MX6, so no point in selecting it again by boards that depend on ARCH_MX6. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* arm: mx6: cm-fx6: move cm-fx6 target under ARCH_MX6Nikita Kiryanov2015-08-02-8/+8
| | | | | | | | | | cm-fx6 is an MX6 based board, and the menuconfig hierarchy should reflect that. Make TARGET_CM_FX6 dependant on ARCH_MX6. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* imx: mx6qp Enable PRG clock for IPUPeng Fan2015-08-02-0/+5
| | | | | | | | | | The i.MX6DQP has a PRG module, need to enable its clock for using IPU. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Brown Oliver <B37094@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* imx: mx6: hab : Remove the cache issue workaroud in hab for i.MX6QPYe.Li2015-08-02-1/+2
| | | | | | | | | Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround for i.MX6QP. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* imx: mx6: ccm: Change the clock settings for i.MX6QPPeng Fan2015-08-02-34/+49
| | | | | | | | | | | | Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes. In c files, use runtime check and discard #ifdef. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* imx: add cpu type for i.MX6QP/DPPeng Fan2015-08-02-5/+16
| | | | | | | | | | | Add cpu type for i.MX6QP/DP. This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP and MXC_CPU_MX6DP, we should use: (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)). Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-07-17-1/+149
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| * Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-07-14-1/+68
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| | * spi: cadence_qspi: add device tree binding docVikas Manocha2015-07-03-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the device tree binding doc for the cadence qspi controller & also removes the not needed properties from the stv0991 device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| | * spi: cadence_qspi: get sram size from device treeVikas Manocha2015-07-03-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| | * stv0991: configure device tree for cadence qspi & flashVikas Manocha2015-07-03-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | This patch add the device tree entry for qspi controller & spi flash memory. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| | * stv0991: enable cadence qspi controller & spi flashVikas Manocha2015-07-03-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | This patch does all the board configurations required to use the qspi controller & attached spi flash memory. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| | * stv0991: configure clock & pad muxing for qspiVikas Manocha2015-07-03-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | stv0991 has cadence qspi controller for flash interfacing, this patch configures the device pads & clock for the controller. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| * | usb: Add EHCI support for Armada 38x (mvebu)Stefan Roese2015-07-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds USB EHCI host support for the common mvebu platform. Including the Armada 38x. Tested on DB-88F6280-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Add SATA/SCSI (AHCI) support for Armada A38xStefan Roese2015-07-10-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the common AHCI controller on the Marvell Armada 38x. Tested on the Marvell DB-88F6820-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Add SDIO/SDHCI support for Armada A38xStefan Roese2015-07-10-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Armada A38x implements an SDHCI compatible SDIO controller. This patch enables the Marvell driver to support this SoC. And enables the SDIO controller if selected by the board configuration. Tested on Marvell DB-88F6820-GP board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | i2c: fix vf610 supportAlbert ARIBAUD \(3ADEV\)2015-07-10-4/+15
| | | | | | | | | | | | | | | | | | | | | Add support in mxc_i2c driver, iomux_v3 and vf610 architecture for the four I2C instances available in VF610. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* | | iMX: adding parsing to hab_status commandUlises Cardenas2015-07-10-13/+245
| | | | | | | | | | | | | | | | | | | | | | | | hab_status command returns a memory dump of the hab event log. But the raw data is not human-readable. Parsing such data into readable event will help to minimize debbuging time. Signed-off-by: Ulises Cardenas <Ulises.Cardenas@freescale.com>
* | | imx: mx6 add i2c4 clock support for i.MX6SXPeng Fan2015-07-10-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C4 clock support for i.MX6SX. Since we use runtime check, but not macro, we need to remove `#ifdef ..` in crm_regs.h, or gcc will fail to compile the code succesfully. Making the macros only for i.MX6SX open to other i.MX6x maybe not a good choice, but we have runtime check. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | | imx: mx6 remove duplicated enable_cspi_clockPeng Fan2015-07-10-20/+0
|/ / | | | | | | | | | | | | | | | | | | enable_spi_clock does the same thing with enable_cspi_clock, so remove enable_cspi_clock. Remove enable_cspi_clock prototype in header file convert cm_fx6/spl.c to use enable_spi_clk Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | sunxi: Adjust Ippo_q8h_v1_2_a33_1024x600 dts filename to match the upstream ↵Hans de Goede2015-07-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | kernel sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dts has been merged into the upstream Linux kernel as sun8i-a33-ippo-q8h-v1.2.dts, adjust u-boot to follow. Note we've never shipped a final u-boot version with the old name, so this is safe todo. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2015-07-07-25/+33
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| * | Revert "break build if it would produce broken binary"Simon Glass2015-07-07-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The root cause of this problem should now be fixed. This reverts commit a6a4c542d316b3401f0840ac5378743191bca851. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Tested-by: Pavel Machek <pavel@denx.de>
| * | arm: Add ENTRY/ENDPROC to private libgcc functionsSimon Glass2015-07-07-17/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_SYS_THUMB_BUILD is defined these functions may be called from Thumb code. Add the required ENTRY and ENDPROC bracketing so that BLX is used to call these ARM functions, instead of plain BL, which will fail. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Pavel Machek <pavel@denx.de>
| * | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-07-07-1437/+3038
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| * | | armv7: better comment in start.SPavel Machek2015-07-07-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix big/small letters in comment. Signed-off-by: Pavel Machek <pavel@denx.de> Tested-by: Marek Vasut <marex@denx.de>
* | | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-07-05-7/+161
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| * | | | sunxi: Add Sinlinx SinA33 defconfigChen-Yu Tsai2015-07-05-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sinlinx SinA33 is a core/daughter board SDK kit from Sinlinx. It has the A33 SoC, USB host, USB OTG, audio input/output, LCD, camera, SDIO and GPIO headers. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: Sync sun8i dts files with the linux kernelChen-Yu Tsai2015-07-05-0/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2. This adds a dts file for Sinlinx SinA33 dev board, and the required changes in the .dtsi files. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: Add support for UART0 in PB pin group on A33Chen-Yu Tsai2015-07-05-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A33 adds a pinmux function for UART0 in the PB pin group. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: rsb: Enable R_PIO clock before configuring external pinsChen-Yu Tsai2015-07-05-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original code was configuring the external pins after enabling the R_PIO clock, which meant the configuration never made it to the pin controller the first time in SPL. Why this was working before is uncertain. Maybe the state was left from a previous boot sequence, or RSB just happened to be the default configuration. However with some A33 chips, SPL failed to configure the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev board. Reordering the calls fixed this. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: hardware-feature-specific function index defines for PORT F UART0Chen-Yu Tsai2015-07-05-4/+4
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 487b327 ("sunxi: GPIO pin mux hardware-feature-specific function index defines") renamed all GPIO index defines, but missed the PORT F UART0 setup functions. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-07-03-10/+19
|\ \ \ \ | |/ / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: configs/tbs2910_defconfig configs/tqma6q_mba6_mmc_defconfig configs/tqma6q_mba6_spi_defconfig configs/tqma6s_mba6_mmc_defconfig configs/tqma6s_mba6_spi_defconfig include/configs/mx6_common.h Signed-off-by: Tom Rini <trini@konsulko.com>
| * | | imx: mx6 introuduce macro is_mx6dqpPeng Fan2015-06-27-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new revision CHIP_REV_2_0. Introudce macro is_mx6dqp, dqp means Dual/Quad Plus. Since Dual/Quad Plus use same cpu type with Dual/Quad, but different revision(Major Lower), we use this macro for Dual/Quad Plus. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | | imx: mx6 correct get_cpu_revPeng Fan2015-06-27-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DIGPROG register map: 23 ------- 16 | 15 ------ 8 | 7 --- 0 | Major upper | Major Lower | Minor | We also need to account for Major Lower. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | | imx: mx6 correct is_soc_rev usagePeng Fan2015-06-27-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | is_soc_rev should return a bool value, so use "==", but not "-", change (is_soc_rev(CHIP_REV_1_0) > 0) to (soc_rev() > CHIP_REV_1_0). This patch also add space between "&" for cpu_type(rev) macro. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | | arm: mx6: tqma6: CPU type selection via KconfigMarkus Niebel2015-06-27-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the first patch to remove the CONFIG_SYS_EXTRA_OPTIONS. This patch implements CPU type selection from Kconfig. Further Kconfig stuff is added later. Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
| * | | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-06-15-111/+137
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| * | | | patch - arm - define SYS_CACHELINE_SIZE for mx5Chris Kuethe2015-06-09-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too Signed-off-by: Chris Kuethe <chris.kuethe@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Matthew Starr <mstarr@hedonline.com> Cc: Andrej Rosano <andrej@inversepath.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Chris Kuethe <chris.kuethe@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | | | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-07-01-0/+35
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| * | | | | zynq: defconfig: Move CONFIG_OF_* to KconfigJagan Teki2015-07-01-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit moves: - CONFIG_OF_CONTROL - SPL_DISABLE_OF_CONTROL from zynq_*_defconfig files into arch/arm/Kconfig "config ARCH_ZYNQ" Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | | | dts: zynq: Enable spi1 for zc770_xm010 boardJagan Teki2015-07-01-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables spi1 for zynq zc770_xm010 board dts Signed-off-by: Jagan Teki <jteki@openedev.com> Tested-by: Jagan Teki <jteki@openedev.com>
| * | | | | spi: zynq_spi: Add fdt support in driverJagan Teki2015-07-01-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now zynq spi driver platform data is controlled by devicetree, enable the status by saying "okay" on respective board dts to use the devicetree generated platdata. Ex: &spi1 { status = "okay"; }; Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
| * | | | | dts: zynq: Add zynq spi controller nodesJagan Teki2015-07-01-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds zynq spi controller nodes in zynq-7000.dtsi. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
generated by cgit v1.1 at 2025-01-04 02:28:11 +0000