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| * | iMX: adding parsing to hab_status commandUlises Cardenas2015-07-10-13/+245
| | | | | | | | | | | | | | | | | | | | | | | | hab_status command returns a memory dump of the hab event log. But the raw data is not human-readable. Parsing such data into readable event will help to minimize debbuging time. Signed-off-by: Ulises Cardenas <Ulises.Cardenas@freescale.com>
| * | imx: mx6 add i2c4 clock support for i.MX6SXPeng Fan2015-07-10-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C4 clock support for i.MX6SX. Since we use runtime check, but not macro, we need to remove `#ifdef ..` in crm_regs.h, or gcc will fail to compile the code succesfully. Making the macros only for i.MX6SX open to other i.MX6x maybe not a good choice, but we have runtime check. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | imx: mx6 remove duplicated enable_cspi_clockPeng Fan2015-07-10-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enable_spi_clock does the same thing with enable_cspi_clock, so remove enable_cspi_clock. Remove enable_cspi_clock prototype in header file convert cm_fx6/spl.c to use enable_spi_clk Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | | armv8: caches: Added routine to set non cacheable regionSiva Durga Prasad Paladugu2015-07-31-10/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-07-29-64/+3567
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| * | | T210: Add support for 64-bit T210-based P2571 boardTom Warren2015-07-28-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on Venice2, incorporates Stephen Warren's latest P2571 pinmux table. With Thierry Reding's 64-bit build fixes, this will build and and boot in 64-bit on my P2571 (when used with a 32-bit AVP loader). Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | P2571: dts: Add DT file for Tegra210 P2571 boardTom Warren2015-07-28-1/+108
| | | | | | | | | | | | | | | | | | | | | | | | Based on T124 Venice2. SDMMC1 is SD-card slot. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: Tegra210: Add support to common Tegra source/config filesTom Warren2015-07-28-39/+453
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Derived from Tegra124, modified as appropriate during T210 board bringup. Cleaned up debug statements to conserve string space, too. This also adds misc 64-bit changes from Thierry Reding/Stephen Warren. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | ARM: Tegra210: Add SoC code/include files for T210Tom Warren2015-07-28-0/+2933
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All based off of Tegra124. As a Tegra210 board is brought up, these may change a bit to match the HW more closely, but probably 90% of this is identical to T124. Note that since T210 is a 64-bit build, it has no SPL component, and hence no cpu.c for Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | Tegra: Rework KConfig options to allow 64-bit builds (T210)Tom Warren2015-07-28-11/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved Tegra config options to mach-tegra/Kconfig so that both 32-bit and 64-bit builds can co-exist for Tegra SoCs. T210 will be 64-bit only (no SPL) and will require a 32-bit AVP/BPMP loader. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | Tegra210: Fix 64-bit build warning about save_boot_params_ret()Tom Warren2015-07-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simon's 'tegra124: Implement spl_was_boot_source()' needs a prototype for save_boot_params_ret() to build cleanly for 64-bit Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: Initialize timer earlierThierry Reding2015-07-28-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A subsequent patch will enable the use of the architected timer on ARMv8. Doing so implies that udelay() will be backed by this timer implementation, and hence the architected timer must be ready when udelay() is first called. The first time udelay() is used is while resetting the debug UART, which happens very early. Make sure that arch_timer_init() is called before that. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: Use standard cache enable for 64-bitThierry Reding2015-07-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 64-bit SoCs the I-cache isn't enabled in early code, so the default cache enable functions for 64-bit ARM can be used. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | ARM: tegra: Restrict usable RAM to 32-bit on 64-bit SoCsThierry Reding2015-07-28-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most peripherals on Tegra can do DMA only to the lower 32-bit address space, even on 64-bit SoCs. This limitation is typically overcome by the use of an IOMMU. Since the IOMMU is not entirely trivial to set up and serves no other purpose (I/O protection, ...) in U-Boot, restrict 64-bit Tegra SoCs to the lower 32-bit address space for RAM. This ensures that the physical addresses of buffers that are programmed into the various DMA engines are valid and don't alias to lower addresses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | armv8/cache: Fix page table creationThierry Reding2015-07-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While generating the page tables, a running integer index is shifted by SECTION_SHIFT (29) and causes overflow for any integer bigger than 7. The page tables therefore alias to the same 8 sections and cause U-Boot to hang once the MMU is enabled. Fix this by making the index a 64-bit unsigned integer and so avoid the overflow. swarren notes: currently "i" ranges from 0..8191 on all ARM64 boards, and "j" varies depending on RAM size; from 4 to 11 for a board with 4GB at physical address 2GB, as some Tegra boards have. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | arm64: Handle arbitrary CONFIG_SYS_MALLOC_F_LEN valuesThierry Reding2015-07-27-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The encoding of the sub instruction used to handle CONFIG_SYS_MALLOC_F_LEN can only accept certain values, and the set of acceptable values differs between the AArch32 and AArch64 instructions sets. The default value of CONFIG_SYS_MALLOC_F_LEN works with either ISA. Tegra uses a non-default value that can only be encoded in the AArch32 ISA. Fix the AArch64 crt0 assembly so it can handle completely arbitrary values. Signed-off-by: Thierry Reding <treding@nvidia.com> [twarren: trimmed Thierry's patch to remove changes already present] Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, cleaned up patch, wrote description, re-wrote subject] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | ARM: tegra: Build warning fixes for 64-bitThierry Reding2015-07-27-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, stripped out changes not strictly related to warnings] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | tegra124: Implement spl_was_boot_source()Simon Glass2015-07-27-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an implementation of this function for Tegra. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-07-28-62/+1238
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| * | | | ARM: zynqmp: Wire up SATA for the boardMichal Simek2015-07-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SATA for the ZynqMP targets. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynqmp: Wire up ethernet controllersMichal Simek2015-07-28-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wire up ethernet controllers and enable MII and BOOTP options. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: Add support for zc770-xm011Michal Simek2015-07-28-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add xm011 DTS file and related configs and configurations. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Update zc770 dtsesMichal Simek2015-07-28-12/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Platform DTSes are missing content needed for platform to be able to use OF binding and DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Add zc702 pushbuttons to DT as gpio-keysMichal Simek2015-07-28-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the two MIO connected pushbuttons on the zc702 board to the devicetree as a single multi-key device for us with the gpio-keys driver. Signed-off-by: Ezra Savard <ezra.savard@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Add missing interrupt for L2 pl310Michal Simek2015-07-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pl310 interrupt to the Zynq devicetree. Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Get rid of ps-clk-frequencyMichal Simek2015-07-28-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ps-clk-frequency is platform specific setting and shouldn't be the part of DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Update years in copyrightMichal Simek2015-07-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trivial. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Sync zc702/zc706/zed/zybo DT with kernelMichal Simek2015-07-28-13/+715
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Syncup with the latest DT from the Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Add reference to bus nodeMichal Simek2015-07-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For adding OCM memory in platform DTS is necessary to have reference to amba bus. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Add pinctrl nodeMichal Simek2015-07-28-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl node to DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Cleanup address-cells and size-cellsMichal Simek2015-07-28-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unneeded address-cells form intc node because it is already setup in parent node. Add missing address-cells and size-cells to eth node to be shared for every platform DTSes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Clean up timer device tree nodesMichal Simek2015-07-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Separate IRQ cells from each other for easier reading. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Use the zynq binding with macbMichal Simek2015-07-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the new zynq binding for macb ethernet, since it will disable half duplex gigabit like the Zynq TRM says to do. Also allow the compatible cadence gem binding that won't disable half duplex but works otherwise. Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Fix GEM register area sizeMichal Simek2015-07-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The size of the GEM's register area is only 0x1000 bytes. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | spi: Fix zynq SPI bindingMichal Simek2015-07-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zynq is using Cadence IP where binding is documented in the Linux kernel and there is no reason to use different binding. Synchronize it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Remove 222 MHz OPPMichal Simek2015-07-28-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to dependencies between timer and CPU frequency, only changes by powers of two are allowed. The clocksource driver prevents other changes, but with cpufreq and its governors it can result in being spammed with error messages constantly. Hence, remove the 222 MHz OPP. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Migrate UART to Cadence bindingMichal Simek2015-07-28-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Zynq UART is Cadence IP and the driver has been renamed accordingly. Migrate the DT to use the new binding for the UART driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Acked-by: Rob Herring <robh@kernel.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Add a fixed regulator for CPU voltageMichal Simek2015-07-28-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To silence the warning cpufreq_cpu0: failed to get cpu0 regulator: -19 from the cpufreq driver regarding a missing regulator, add a fixed regulator to the DT. Zynq does not support voltage scaling and the CPU rail should always be supplied with 1 V, hence it is added in the SOC-level dtsi. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Add missing nodes to DTSIMichal Simek2015-07-28-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ADC, CAN, GPIO, MC, DMA, DEVCFG, USB, Watchdog IPs to DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Use the right names for nodesMichal Simek2015-07-28-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on SPEC you right names with addresses. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | zynqmp: Add support for IP detection via SLCRMichal Simek2015-07-28-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SLCR can be used for IP configuration setting. Add SLCR skeleton to enable run time checking. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | zynqmp: mp: Simplify set_r5_start handlingMichal Simek2015-07-28-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pass directly boot_addr which is LOVEC (0) or HIVEC (0xffff0000). No reason to use magic values 0 and 1. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | zynqmp: Define ep config for ZynqMPSiva Durga Prasad Paladugu2015-07-28-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a new config "zynqmp_ep" for ZynqMP instead of xilinx_zynqmp. This defconfig supports all emulation platforms of ZynqMP. Also renamed TARGET_XILINX_ZYNQMP to ARCH_ZYNQMP. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | zynqmp: Kconfig: Move zynqmp KconfigSiva Durga Prasad Paladugu2015-07-28-1/+17
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the zynqmp Kconfig from board to arch as there may be different boards under same architecture. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | stm32f4: add cpu clock option for 180 MHzAntonio Borneo2015-07-27-10/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While most stm32f4 run at 168 MHz, stm32f429 can work till 180 MHz. Add option to select 180 MHz through macro CONFIG_SYS_CLK_FREQ. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> To: Albert Aribaud <albert.u.boot@aribaud.net> To: Tom Rini <trini@konsulko.com> To: Kamil Lulko <rev13@wp.pl> Cc: u-boot@lists.denx.de
* | | | stm32f429: pass the device unique ID in DTBAntonio Borneo2015-07-27-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read device unique ID and set environment variable "serial#". Value would then be passed to kernel through DTB. To read ID from DTB, kernel is required to have commit: 3f599875e5202986b350618a617527ab441bf206 (ARM: 8355/1: arch: Show the serial number from devicetree in cpuinfo) This commit is already mainline since v4.1-rc1. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> To: Albert Aribaud <albert.u.boot@aribaud.net> To: Tom Rini <trini@konsulko.com> To: Kamil Lulko <rev13@wp.pl> Cc: u-boot@lists.denx.de
* | | | Kill unneeded #include <linux/kconfig.h>Masahiro Yamada2015-07-27-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because the top-level Makefile forces all the source files to include include/linux/kconfig.h (see the UBOOTINCLUDE define), these includes are redundant. By the way, there are exceptions for the statement above; host programs. In fact, host tools in U-Boot depend on a particular board configuration, although I think they should not. So, some files still include <linux/config.h> to work around build errors on host tools. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Simon Glass <sjg@chromium.org>
* | | | am33xx: Unused get_board_rev function removalPaul Kocialkowski2015-07-27-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All am33xx device tree are using device-tree, so get_board_rev is never actually called. Thus, we can get rid of it to make the code easier to maintain. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | omap3: CONFIG_REVISION_TAG ifdef check for get_board_revPaul Kocialkowski2015-07-27-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Despite being defined with __weak, this declaration of get_board_rev will conflict with the fallback one when ONFIG_REVISION_TAG is not defined. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | omap5: Definitions for SYS_BOOT-based fallback boot device selectionPaul Kocialkowski2015-07-27-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This introduces code to read the value of the SYS_BOOT pins on the OMAP5, as well as the memory-preferred scheme for the interpretation of each value. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
generated by cgit v1.1 at 2024-09-23 06:29:10 +0000