| Commit message (Collapse) | Author | Age | Lines |
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- Initialize PLLs (SPL initializes only DPLL to save the precious
SPL memory footprint)
- Adjust CPLL/MPLL to the final tape-out frequency
- Set the Cortex-A53 clock to the maximum frequency since it is
running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot
proper. Split the common code into pll-base-ld20.c for easier
re-use.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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The System Control block moved to a completely different register
map for ARMv8 SoCs, so it cannot be shared with the ARM 32-bit ones.
Define register macros in a new header file.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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