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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-09-17 03:33:11 +0900 |
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committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-09-19 00:12:26 +0900 |
commit | 682e09ff9f3514e79ee3382988b74f63b4bdd06b (patch) | |
tree | f0ad6ed0c890bebd7bd627b29be27c1ebd9d64a0 /arch/arm/mach-uniphier/sc64-regs.h | |
parent | fcc238baee1495ff9796dfc4e13f8069a152e85f (diff) | |
download | u-boot-imx-682e09ff9f3514e79ee3382988b74f63b4bdd06b.zip u-boot-imx-682e09ff9f3514e79ee3382988b74f63b4bdd06b.tar.gz u-boot-imx-682e09ff9f3514e79ee3382988b74f63b4bdd06b.tar.bz2 |
ARM: uniphier: add PLL init code for LD20 SoC
Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot
proper. Split the common code into pll-base-ld20.c for easier
re-use.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/sc64-regs.h')
-rw-r--r-- | arch/arm/mach-uniphier/sc64-regs.h | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h index ef02830..1e52bb1 100644 --- a/arch/arm/mach-uniphier/sc64-regs.h +++ b/arch/arm/mach-uniphier/sc64-regs.h @@ -1,7 +1,8 @@ /* * UniPhier SC (System Control) block registers for ARMv8 SoCs * - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -11,6 +12,25 @@ #define SC_BASE_ADDR 0x61840000 +/* PLL type: SSC */ +#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* LD20: CPU/ARM */ +#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* LD20: misc */ +#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* LD20: IPP */ +#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* LD20: Video codec */ +#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD20: VPE etc. */ +#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* LD20: GPU/Mali */ +#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* LD20: DDR memory 0 */ +#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* LD20: DDR memory 1 */ +#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* LD20: DDR memory 2 */ + +/* PLL type: VPLL27 */ +#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) + +/* PLL type: DSPLL */ +#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) +#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0) + #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) |