Commit message (Expand) | Author | Age | Lines | |
---|---|---|---|---|
* | ARM: tegra210: implement PLLE init procedure from TRM | Stephen Warren | 2015-11-12 | -47/+132 |
* | ARM: tegra: clk_m is the architected timer source clock | Thierry Reding | 2015-09-16 | -6/+4 |
* | ARM: tegra: Implement clk_m | Thierry Reding | 2015-09-16 | -0/+11 |
* | tegra: Correct logic for reading pll_misc in clock_start_pll() | Simon Glass | 2015-08-13 | -0/+7 |
* | Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. | Tom Warren | 2015-08-05 | -1/+30 |
* | Tegra: clocks: Add 38.4MHz OSC support for T210 use | Tom Warren | 2015-08-05 | -2/+6 |
* | ARM: Tegra210: Add SoC code/include files for T210 | Tom Warren | 2015-07-28 | -0/+1091 |