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* arm: mvebu: Implement secure bootMario Six2017-02-01-0/+371
| | | | | | | | | | | | | | | | | | | | | The patch implements secure booting for the mvebu architecture. This includes: - The addition of secure headers and all needed signatures and keys in mkimage - Commands capable of writing the board's efuses to both write the needed cryptographic data and enable the secure booting mechanism - The creation of convenience text files containing the necessary commands to write the efuses The KAK and CSK keys are expected to reside in the files kwb_kak.key and kwb_csk.key (OpenSSL 2048 bit private keys) in the top-level directory. Signed-off-by: Reinhard Pfau <reinhard.pfau@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
* arm: mvebu: spl.c: Remove useless gd declarationReinhard Pfau2017-02-01-2/+0
| | | | | | | | | | | | ddaa905 ("arm: mvebu: Add DM (driver model) support") removed the assignment of the gd pointer, but kept the (now superfluous) declaration of the gd pointer. Remove this declaration. Signed-off-by: Reinhard Pfau <pfau@gdsys.de> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* mvebu: Add board_pex_config()Mario Six2017-02-01-0/+10
| | | | | | | | | Allow boards to do some initialization when PCIe comes up. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* pci: mvebu: Fix Armada 38x supportDirk Eibach2017-02-01-0/+1
| | | | | | | | | | | | Armada 38x has four PCI ports, not three. The optimization in pci_init_board() seems to assume that every port has three lanes. This is obviously wrong, and breaks support for Armada 38x. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* Convert CONFIG_ARCH_MISC_INIT to KconfigSimon Glass2017-01-25-0/+1
| | | | | | | This converts the following to Kconfig: CONFIG_ARCH_MISC_INIT Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_BOARD_EARLY_INIT_F to KconfigSimon Glass2017-01-25-0/+1
| | | | | | | This converts the following to Kconfig: CONFIG_BOARD_EARLY_INIT_F Signed-off-by: Simon Glass <sjg@chromium.org>
* Kconfig: Migrate BOARD_LATE_INIT to a selectTom Rini2017-01-24-0/+2
| | | | | | | | | This option should not really be user selectable. Note that on PowerPC we currently only need BOARD_LATE_INIT when CHAIN_OF_TRUST is enabled so be conditional on that. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> (for UniPhier)
* mmc: move some SDHCI related options to KconfigMasahiro Yamada2016-12-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While I moved the options, I also renamed them so that they are all prefixed with MMC_SDHCI_. This commit was created in the following steps. [1] Rename with the following command find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \ -type f -print | xargs sed -i -e ' s/CONFIG_MMC_SDMA/CONFIG_MMC_SDHCI_SDMA/g s/CONFIG_BCM2835_SDHCI/CONFIG_MMC_SDHCI_BCM2835/g s/CONFIG_KONA_SDHCI/CONFIG_MMC_SDHCI_KONA/g s/CONFIG_MV_SDHCI/CONFIG_MMC_SDHCI_MV/g s/CONFIG_S5P_SDHCI/CONFIG_MMC_SDHCI_S5P/g s/CONFIG_SPEAR_SDHCI/CONFIG_MMC_SDHCI_SPEAR/g ' [2] create the Kconfig entries in drivers/mmc/Kconfig [3] Move the options by the following command tools/moveconfig.py -y MMC_SDHCI_SDMA MMC_SDHCI_BCM2835 \ MMC_SDHCI_KONA MMC_SDHCI_MV MMC_SDHCI_S5P MMC_SDHCI_SPEAR [4] Sort drivers/mmc/Makefile for readability Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* arm64: mvebu: Fix A8K memory mapping and add documentationKonstantin Porotchkin2016-12-21-13/+45
| | | | | | | | | | | | | | | | | | | | Fix the MMU mapping for A8K device family: - Separate A7K and A8K memory mappings - Fix memory regions by including IO mapping for all 3 PCIe interfaces existing on each connected CP110 controller Add A8K memory mapping documentation with all regions configured by Marvell ATF. Change-Id: I9c930569b1853900f5fba2d5db319b092cc7a2a6 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* arm64: mvebu: Add L3 cache flush functionality to A8K familyKonstantin Porotchkin2016-12-12-0/+40
| | | | | | | | | | | | | | | | | | | | | | | Add missing L3 cache flush functionality which absence prevents Linux kernel from normal boot in case the L3 cache is enabled by ATF. The L3 cache is named the "last level" cache in order to keep the terminology similar to the ATF code. This cache should not be disabled by u-boot since the Linux kernel cannot activate it, so it is activates at ATF stage. However the cache flush is required for preventing data corruption after disabling the MMU and the data cache before passing control to the loaded Linux image. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* arm64: mvebu: Restrict memory size to a usable maximumStefan Roese2016-12-05-0/+17
| | | | | | | | | | | | | | | | | Not all memory is mapped in the MMU. So we need to restrict the memory size so that U-Boot does not try to access it. Also, the internal registers are located at 0xf000.0000 - 0xffff.ffff. Currently only 2GiB are mapped for system memory. This is what we pass to the U-Boot subsystem here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* arm64: mvebu: Add regions for PCI spaces to the memory mapStefan Roese2016-12-05-0/+8
| | | | | | | | | | | | | | To use the PCIe driver, its controller memory and the PCIe regions need to get mapped in the MMU. Otherwise these areas can't be accessed. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* arm64: mvebu: Init COMPHY from the slave-CP on the A8kStefan Roese2016-12-05-6/+14
| | | | | | | | | | | | | | | | The Armada8k implements 2 CPs (communication processors) and the 2nd CP also is equipped with a COMPHY controller. This patch now loops over all enabled MISC devices (CP110) enabled in the DT to initialize all CPs. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* arm64: mvebu: Add slave CP area to the memory mapStefan Roese2016-12-05-1/+9
| | | | | | | | | | | | | | To enable access to the slave CP its memory needs to be added to the MMU memory map. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* arm64: mvebu: Rename db-88f7040 files to armada-8kStefan Roese2016-12-05-5/+5
| | | | | | | | | | | | | | | | | This moves some of the Armada DB-88F7040 board specific files to a more generic name: armada-8k. This is in preparation for the Armada-8k support which will be added soon. And since both platforms share most devices, lets also share most source files to not duplicate the code here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* arm: mvebu: move SYS_MVEBU_PLL_CLOCK to KconfigChris Packham2016-12-01-3/+6
| | | | | | | | | | The main PLL frequency is 2GHz for Armada-XP and 1GHZ for Armada 375, 38x and 39x. [ Linux commit ae142bd9976532aa5232ab0b00e621690d8bfe6a ] Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* arm64: mvebu: Add Armada 7K db-88f7040 development board supportStefan Roese2016-09-27-0/+7
| | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the Marvell Armada 7K DB-88F7040 development board. Supported are the following interfaces: - UART - SPI (incl. SPI NOR) - I2C - USB - SATA / AHCI Support for other interfaces will follow. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* arm64: mvebu: Add basic support for the Marvell Armada 7K/8K SoCStefan Roese2016-09-27-109/+215
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Compared to the Armada 3700, the Armada 7K and 8K are much more on the high-end side: they use a dual Cortex-A72 or a quad Cortex-A72, as opposed to the Cortex-A53 for the Armada 3700. The Armada 7K and 8K also use a fairly unique architecture, internally they are composed of several components: - One AP (Application Processor), which contains the processor itself and a few core hardware blocks. The AP used in the Armada 7K and 8K is called AP806, and is available in two configurations: dual Cortex-A72 and quad Cortex-A72. - One or two CP (Communication Processor), which contain most of the I/O interfaces (SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP, while the 8K family chips integrate two CPs, providing two times the number of I/O interfaces available in the CP. The CP used in the 7K and 8K is called CP110. All in all, this gives the following combinations: - Armada 7020, which is a dual Cortex-A72 with one CP - Armada 7040, which is a quad Cortex-A72 with one CP - Armada 8020, which is a dual Cortex-A72 with two CPs - Armada 8040, which is a quad Cortex-A72 with two CPs This patch adds basic support for this ARMv8 based SoC into U-Boot. Future patches will integrate other device drivers and board support, starting with the Marvell DB-88F7040 development board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* arm64: mvebu: Add Armada 3700 db-88f3720 development board supportStefan Roese2016-09-27-0/+7
| | | | | | | | | | | | | | | | | | | This patch adds basic support for the Marvell Armada 3700 DB-88F3720 development board. Supported are the following interfaces: - UART - SPI (incl. SPI NOR) - I2C - Ethernet Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
* arm64: mvebu: Add support for the Marvell Armada 3700 SoCStefan Roese2016-09-27-6/+284
| | | | | | | | | | | | | | | | | | | | | | | | The Armada 3700 integrates the following interfaces (not complete list): - Dual Cortex-A53 ARMv8 - USB 3.0 - SATA 3.0 - PCIe 2.0 - 2 x Gigabit Ethernet 1Gbps / 2.5Gbps - ... This patch adds basic support for this ARMv8 based SoC into U-Boot. Future patches will integrate other device drivers and board support for the Marvell DB-88F3720 development board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
* arm: mvebu: add DB-88F6820-AMC boardChris Packham2016-09-24-0/+7
| | | | | | | | | | | | | | | This board is a plug in card for Marvell's switch system development kits. Form-factor aside it is similar to the DB-88F6820-GP with the following differences. - TCLK is 200MHz - SPI1 is used - No SATA - No MMC - NAND flash Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* arm: mvebu: create generic 88F6820 config optionChris Packham2016-09-24-4/+4
| | | | | | | | | | | | | 88F6820 is a specific Armada-38x chip that is used on the DB-88F6820-GP board. Rather than having DB_88F6820_GP and TARGET_DB_88F6820_GP which selects the former. Rename DB_88F6820_GP to 88F6820 so that other boards using the 88F6820 can be added. Stefan: Change 88F6820 for clearfog as well. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-23-1/+1
| | | | | | | | | | | Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: Move SYS_CACHELINE_SIZE over to KconfigTom Rini2016-08-26-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: Paul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: "Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Chin Liang See <clsee@altera.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Paul Kocialkowski <contact@paulk.fr>
* arm: mvebu: a38x: typo fix cpabilities -> capbilitiesChris Packham2016-08-26-1/+1
| | | | | Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* arm: mvebu: a38x: update serdes error handlingChris Packham2016-08-26-19/+20
| | | | | | | | | Ensure appropriate error messages are generated. Previously all errors indicated that the serdes was already in use. Now appropriate error messages are given. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* arm: mvebu: Add support for NAND interface on A-38xChris Packham2016-08-26-1/+10
| | | | | | | | | | | The NAND interface on the Armada-38x series is similar to that on the Armada-XP. The key difference is that the NAND ECC clock ratio is provided via the DFX Server registers instead of the Core Clock. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* common: Pass the boot device into spl_boot_mode()Marek Vasut2016-06-26-1/+1
| | | | | | | | | | | | | | | | | | The SPL code already knows which boot device it calls the spl_boot_mode() on, so pass that information into the function. This allows the code of spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets board_boot_order() correctly alter the behavior of the boot process. The later one is important, since in certain cases, it is desired that spl_boot_device() return value be overriden using board_boot_order(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [add newly introduced zynq variant] Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>
* configs: Re-sync with cmd/KconfigTom Rini2016-04-25-1/+0
| | | | | | | Update the config.h and defconfig files for the commands that 8e3c036 converted over to Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: mvebu: Add base address for 2nd I2C controllerStefan Roese2016-04-12-0/+1
| | | | | | | Add MVEBU_TWSI1_BASE define so that the 2nd I2C controller on e.g. AXP can be used. Signed-off-by: Stefan Roese <sr@denx.de>
* arm: mvebu: Don't enable d-cache on A375Stefan Roese2016-04-04-2/+9
| | | | | | | | Armada 375 still has some problems with d-cache enabled in the ethernet driver (mvpp2). So lets keep the d-cache disabled until this is solved. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Add basic support for Armada 375 eval board db-88f6720Stefan Roese2016-04-04-1/+11
| | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the Marvell A375 eval board. Tested are the following interfaces: - I2C - SPI - SPI NOR - Ethernet (mvpp2), port 0 & 1 Currently the A375 SerDes and DDR3 init code is not intergrated. So the SPL U-Boot is not fully functional. Right now, this A375 mainline U-Boot can only be used by chainloading it via the original Marvell U-Boot. This can be done via this command: => tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000 Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Add basic support for the Marvell Armada 375 SoCStefan Roese2016-04-04-5/+92
| | | | | | | | | | | | | | | This patch adds basic support for the Armada 375. Please note that currently the SerDes and DDR3 init code for the A375 is not included / enabled. This will be done in a later, follow-up patch. Right now, this A375 mainline U-Boot can only be used by chainloading it via the original Marvell U-Boot. This can be done via this command: => tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000 Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Add some SPI CS attributesStefan Roese2016-03-24-0/+3
| | | | | | | | | | These attribute defines may be used to map an area of memory for direct access to the specific SPI devices. See SPI Direct Access Mode for further information. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
* arm: mvebu: Add support for the Armada XP theadorable boardStefan Roese2016-01-27-0/+6
| | | | | | | | | | | | | | | | | | | This patch adds support for the Armada XP (MV78260) based theadorable board. Its equipped with onboard DDR3, UART, ethernet, I2C, SPI NOR, LCD and SATA (SSD) interfaces / devices. Two defconfigs are added: theadorable_defconfig: The production U-Boot version with a stripped down drivers and feature list. This removes networking, USB and PCI support. theadorable_debug_defconfig: The debugging / testing U-Boot version with full support for all drivers. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
* video: Add support for Armada XP LCD controllerStefan Roese2016-01-23-0/+14
| | | | | | | | | | | | | | This patch adds basic support for the LCD controller of the Marvell Armada XP SoC. An AXP based custom board port will be added later, to use this driver to display a splash screen via the bmp command later. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> [agust: rebased] Signed-off-by: Anatolij Gustschin <agust@denx.de>
* mvebu: Support Synology DS414Phil Sutter2016-01-14-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the MV78230 based DS414 NAS by Synology. The relevant bits have been extracted from the 'synogpl-5004-armadaxp' package Synology kindly published, garnished with a fair amount of trial-and-error. Sadly, support is far from perfect. The major parts I have failed in are SATA and XHCI support. Details about these and some other things follow: Device Tree ----------- The device tree file armada-xp-synology-ds414.dts has been copied from Linux and enhanced by recent U-Boot specific changes to armada-xp-gp.dts. SATA Support ------------ There is a Marvell 88SX7042 controller attached to PCIe which is supported by Linux's sata_mv driver but sadly not U-Boot's sata_mv. I'm not sure if extending the latter to support PCI devices is worth the effort at all. Porting sata_mv from Linux exceeded my brain's capacities. :( XHCI Support ------------ There is an EtronTech EJ168A XHCI controller attached to PCIe which drives the two rear USB3 ports. After a bit of playing around I managed to get it recognized by xhci-pci, but never was able to access any devices attached to it. Enabling it in ds414 board config shows that it does not respond to commands for whatever reason. The (somewhat) bright side to it is that it is not even supported in Synology's customized U-Boot, but that also means nowhere to steal the relevant bits from. EHCI Support ------------ This seems functional after issuing 'usb start'. At least it detects USB storage devices, and IIRC reading from them was OK. OTOH Linux fails to register the controller if 'usb start' wasn't given before in U-Boot. According to Synology sources, this board seems to support USB device (gadget?) mode. Though I didn't play around with it. PCIe Support ------------ This is fine, but trying to gate the clocks of unused lanes will hang PCI enum. In addition to that, pci_mvebu seems not to support DM_PCI. DDR3 Training ------------- Marvell/Synology uses eight PUPs instead of four. Does not look like this is meant to be customized in mainline U-Boot at all. OTOH I have no idea what a "PUP" actually is. PEX Init -------- Synology uses different values than mainline U-Boot with this patch: pex_max_unit_get returns 2, pex_max_if_get returns 7 and max_serdes_lines is set to 7. Not changing this seems to not have an impact, although I'm not entirely sure it does not cause issues I am not aware of. Static Environment ------------------ This allows to boot stock Synology firmware at least. In order to be a little more flexible when it comes to booting custom kernels, do not only load zImage partition, but also rd.gz into memory. This way it is possible to use about 7MB for kernel with piggyback initramfs. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* mvebu: Add rudimental MV78230 supportPhil Sutter2016-01-14-6/+17
| | | | | | | | | This adds basic support for Marvell's MV78230 SoC which belongs to the Armada XP series. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* mvebu: Introduce kconfig symbols for SoC variantsPhil Sutter2016-01-14-4/+20
| | | | | | | | | This patch adds intermediate kconfig symbols which select their SoC family. Boards then select them instead of the family symbol directly. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* mvebu: axp: refactor board_sat_r_get() and callerPhil Sutter2016-01-14-31/+15
| | | | | | | | | | | | | Instead of calling board_sat_r_get() only for those boards providing the satr11 value via I2C, call it for all boards and return static values for those not using I2C. In addition to that, make this a weak function to allow for board code to override it. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* drivers/pci/pci_mvebu: Fix for boards with X4 lanesPhil Sutter2016-01-14-0/+2
| | | | | | | | | | | | | | | | | Armada XP has support for X4 lanes, boards specify this in their serdes_cfg. During PEX init in high_speed_env_lib.c, the configuration is stored in GEN_PURP_RES_2_REG. When enumerating PEX, subsequent interfaces of an X4 lane must be skipped. Otherwise the enumeration hangs up the board. The way this is implemented here is not exactly beautiful, but it mimics how Marvell's BSP does it. Alternatively we could get the information using board_serdes_cfg_get(), but that won't lead to clean code, either. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: mvebu: Add runtime detection of UART (xmodem) boot-modeStefan Roese2016-01-14-20/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds runtime detection of the Marvell UART boot-mode (xmodem protocol). If this boot-mode is detected, SPL will return to the BootROM to continue the UART booting. With this patch its now possible, to generate a U-Boot image that can be booted either from the strapped boot-device (e.g. SPI NOR, MMC, etc) or via the xmodem protocol from the UART. In the UART case, the kwboot tool will dynamically insert the UART boot-device type into the image. And also patch the load address in the header, so that the mkimage header will be skipped (as its not expected by the Marvell BootROM). This simplifies the development for Armada XP / 38x based boards. As no special images need to be generated by selecting the MVEBU_BOOTROM_UARTBOOT Kconfig option. Since the Kconfig option MVEBU_BOOTROM_UARTBOOT is not needed any more, its now completely removed. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Phil Sutter <phil@nwl.cc> Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
* arm: mvebu: Add runtime boot-device detectionStefan Roese2016-01-14-7/+39
| | | | | | | | | | This patch adds runtime boot-device detection to SPL U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Phil Sutter <phil@nwl.cc> Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
* arm: mvebu: Make local structs static constStefan Roese2016-01-14-2/+2
| | | | | | | | | | As these structs are local only and const, declare them accordingly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Phil Sutter <phil@nwl.cc> Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
* arm: mvebu: Move SAR register defines into headerStefan Roese2016-01-14-16/+24
| | | | | | | | | | This is preparation for the runtime bootmode detection in spl.c. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Phil Sutter <phil@nwl.cc> Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
* arm: mvebu: Move SoC selection (A38X vs AXP) into KconfigStefan Roese2016-01-14-14/+25
| | | | | | | | | | | | | | | | | | Until now, the SoC selection for the ARCH_MVEBU platforms has been done in the config header. Using CONFIG_ARMADA_XP in a non-clear way. As it needed to get selected for AXP and A38x based boards. This patch now changes this to move the SoC selection to Kconfig. And also uses CONFIG_ARCH_MVEBU as a common define for both AXP and A38x. This makes things a bit clearer - especially for new board additions. Additionally the defines CONFIG_SYS_MVEBU_DDR_AXP and CONFIG_SYS_MVEBU_DDR_A38X are replaced with the already available CONFIG_ARMADA_38X and CONFIG_ARMADA_XP. And CONFIG_DDR3 is removed, as its not referenced anywhere. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Consolidate board Kconfig options into one fileStefan Roese2016-01-14-0/+17
| | | | | | | | Merging all the board specific Kconfig options into the main Kconfig file for mach-mvebu makes things easier to maintain. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Print CPU and SDRAM frequency upon startupStefan Roese2016-01-14-8/+113
| | | | | | | | | | | | | | | With this patch, the CPU and the DDR frequencies will get printed in the U-Boot startup messages. Resulting in such a log: U-Boot 2016.01-rc2-00188-gb8eeaec-dirty (Dec 21 2015 - 12:32:35 +0100) SoC: MV78460-B0 at 1600 MHz I2C: ready DRAM: 4 GiB (800 MHz, ECC not enabled) ... Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Make serdes setup on Armada XP less noisyStefan Roese2016-01-14-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change some of the PEX configuration output lines from always output to only ouput upon specific debug enabling. This changes the SPL output from: U-Boot SPL 2016.01-rc2-00037-g9353a7f (Dec 10 2015 - 10:27:42) High speed PHY - Version: 2.1.5 (COM-PHY-V20) Update Device ID PEX0782611ab Update Device ID PEX1782611ab Update Device ID PEX2782611ab Update Device ID PEX3782611ab Update Device ID PEX8782611ab Update PEX Device ID 0x78260 High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.4 DDR3 Training Sequence - Ended Successfully to: U-Boot SPL 2016.01-rc2-00037-g9353a7f-dirty (Dec 10 2015 - 10:32:04) High speed PHY - Version: 2.1.5 (COM-PHY-V20) High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.4 DDR3 Training Sequence - Ended Successfully Resulting in a little faster bootup time. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Don't include "netdev.h" in cpu.cStefan Roese2016-01-14-1/+0
| | | | | | | | | This is not needed any more since the switch to DM / DTS network initialization on MVEBU. Lets remove it, as it otherwise leads to compilation warning when CONFIG_NET is not enabled. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
generated by cgit v1.1 at 2024-11-01 11:31:37 +0000