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| author | Phil Sutter <phil@nwl.cc> | 2015-12-25 14:41:20 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2016-01-14 14:08:59 +0100 |
| commit | 9a04527840dbb2c7b8bc5bd5145fa9bd26c597b4 (patch) | |
| tree | 5ccc51a1f1823cd98d6ea6fb45256ede22d42f0c /arch/arm/mach-mvebu | |
| parent | 7e1e59a7b7da45361761ab1439c2751f4cae4163 (diff) | |
| download | u-boot-imx-9a04527840dbb2c7b8bc5bd5145fa9bd26c597b4.zip u-boot-imx-9a04527840dbb2c7b8bc5bd5145fa9bd26c597b4.tar.gz u-boot-imx-9a04527840dbb2c7b8bc5bd5145fa9bd26c597b4.tar.bz2 | |
drivers/pci/pci_mvebu: Fix for boards with X4 lanes
Armada XP has support for X4 lanes, boards specify this in their
serdes_cfg. During PEX init in high_speed_env_lib.c, the configuration
is stored in GEN_PURP_RES_2_REG.
When enumerating PEX, subsequent interfaces of an X4 lane must be
skipped. Otherwise the enumeration hangs up the board.
The way this is implemented here is not exactly beautiful, but it mimics
how Marvell's BSP does it. Alternatively we could get the information
using board_serdes_cfg_get(), but that won't lead to clean code, either.
Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/mach-mvebu')
| -rw-r--r-- | arch/arm/mach-mvebu/include/mach/soc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index c696fc6..9f6a2a4 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -96,6 +96,8 @@ #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE +#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8)) + /* BootROM error register (also includes some status infos) */ #define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) #define BOOTROM_ERR_MODE_OFFS 28 |