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* tegra20: port to new ehci interfaceLucas Stach2012-10-15-2/+2
| | | | | | | EHCI interface now supports more than one controller. Wire up our usb functions to use this new interface. Signed-off-by: Lucas Stach <dev@lynxeye.de>
* usb: ehci: rework to take advantage of new lowlevel interfaceLucas Stach2012-10-15-1/+9
| | | | | | | | | | | | | | Kill off ehci-core.h It was used to specify some static controller data. To support more than one controller being active at any time we have to carry the controller data ourselfes. Change the ehci interface accordingly. NOTE: OMAP implemented the ehci stuff a bit backwards and should be fixed to do the same thing as other platforms. But the change for now is at least compile clean. Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Marek Vasut <marex@denx.de>
* ARM: Add Altera SOCFPGA Cyclone5Dinh Nguyen2012-10-04-0/+119
| | | | | | | | | | | | | | | | | Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Tom Trini <trini@ti.com> Cc: Wolfgang Denx <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> ---- v8: Remove no_return attribute for reset_cpu Based on v2012.10-rc2
* Merge remote-tracking branch 'u-boot-marvell/master'Albert ARIBAUD2012-10-03-3/+2
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| * ARM: kirkwood/orion5x: Use reset_cpu definition in include/common.hDinh Nguyen2012-10-03-2/+0
| | | | | | | | | | | | | | | | | | include/common.h has the reset_cpu defined already. No need to re-define here. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Acked-By: Prafulla Wadaskar <Prafulla@marvell.com>
| * kirkwood: implement kw_sdram_size_adjustGerlando Falauto2012-10-03-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Size of the SDRAM chips might differ between any two (otherwise identical) instances of the same board. So add a function kw_sdram_size_adjust() which reads out the current ram size for a given bank, and adjusts the Kirkwood's SDRAM window size register accordingly. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com>
| * kirkwood: fix mpp.h coding styleLuka Perkov2012-10-03-1/+1
| | | | | | | | Signed-off-by: Luka Perkov <uboot@lukaperkov.net>
* | ARM : Add GPIO Driver and IOMUX definition for S3C2440Gabriel Huau2012-10-03-0/+371
|/ | | | | | | It's now possible to use the gpio driver interface for s3c2440. This patch add iomux definitions too. Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
* arm: rmobile: Add support for ATMARK-TECHNO Armadillo-800EVA boardHideyuki Sano2012-10-03-0/+13
| | | | | | | | | | | | | | The Armadillo-800EVA board has Renesas R-Mobile R8A7740, 512MB DDR3-SDRAM, Ethernet, and more. This patch supports the following functions: - 512MB DDR3-SDRAM - Serial console (SCIF) - Ethernet MAC(MII) & PHY(SMSC) Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* arm: rmobile: Add support PFC of Renesas R8A7740Nobuhiro Iwamatsu2012-10-03-0/+587
| | | | | | | | | Renesas R8A7740 has GPIO based PFC. This privode framework of PFC. The code included in this base from linux kernel. Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* arm: rmobile: Add support Renesas R8A7740Nobuhiro Iwamatsu2012-10-03-0/+307
| | | | | | | | | Renesas R8A7740 is CPU with Cortex-A9. This supports the basic register definition and GPIO. Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* arm: rmobile: kzm9g: Add dummy member to struct sh73a0_rwdtTetsuyuki Kobayashi2012-10-03-0/+2
| | | | | | | | Add dummy member to struct sh73a0_rwdt in sh73a0.h. Without this, initializing watch dog timer goes wrong. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* arm: rmobile: kzm9g: enable reset commandTetsuyuki Kobayashi2012-10-03-0/+4
| | | | | | | Do soft power on reset in U-Boot reset command. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* arm: rmobile: kzm9g: Adjust low level hardware settingTetsuyuki Kobayashi2012-10-03-1/+3
| | | | | | | Adjust low level hardware setting in s_init. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* arm: rmobile: Add supoprt for KMC KZM-A9-GT boardNobuhiro Iwamatsu2012-10-03-0/+13
| | | | | | | | | | | | | | | The KZM-A9-GT board has Renesas R-Mobile SH73A0, 512MB DDR2-SDRAM, USB, Ethernet, and more. This patch supports the following functions: - 512MB DDR2-SDRAM - 16MB NOR Flash memory - Serial console (SCIF) - Ethernet (SMSC) - I2C Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* arm: rmobile: Add support PFC of Renesas SH73A0Nobuhiro Iwamatsu2012-10-03-0/+9
| | | | | | | | Renesas SH73A0 has GPIO based PFC. This privode framework of PFC. The code included in this base from linux kernel. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* arm: rmobile: Add support Renesas SH73A0Nobuhiro Iwamatsu2012-10-03-0/+867
| | | | | | | | Renesas SH73A0 is CPU with Cortex-A9. This supports the basic register definition and GPIO. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* arm: rmobile: Add basic support for Renesas R-MobileNobuhiro Iwamatsu2012-10-03-0/+8
| | | | | | | | This patch adds minimum support for R-Mobile. Only minimal support with timer. This CPU can uses the peripheral of Renesas SuperH. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* ARMv7: Add register definition of global timerNobuhiro Iwamatsu2012-10-03-0/+36
| | | | | | | ARMv7 has global timer. This provides the register definition of this timer. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* am33xx: Fix fetching of mmc1 bootmode from bootrom for AM33XXJoel A Fernandes2012-10-01-0/+1
| | | | | | | | | | | U-boot should not ignore getting the bootmode passed on from the bootrom. With this, U-boot SPL knows it was loaded from MMC1 and use this info to read full U-boot from MMC1 as well. Cc: pprakash@ti.com Cc: trini@ti.com Signed-off-by: Joel A Fernandes <joelagnel@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* OMAP: networking support for SPLIlya Yanok2012-10-01-0/+1
| | | | | | | | | | | | | | This patch adds support for networking in SPL. Some devices are capable of loading SPL via network so it makes sense to load the main U-Boot binary via network too. This patch tries to use existing network code as much as possible. Unfortunately, it depends on environment which in turn depends on other code so SPL size is increased significantly. No effort was done to decouple network code and environment so far. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Tom Rini <trini@ti.com>
* Merge remote-tracking branch 'u-boot/master'Albert ARIBAUD2012-09-30-94/+366
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| * ARM: SPL: Convert davinci to CONFIG_SPL_FRAMEWORKTom Rini2012-09-27-0/+32
| | | | | | | | | | | | | | | | - Convert the non-relocation part of board_init_f to spl_board_init, turn on CONFIG_SPL_BOARD_INIT in the configs. - Remove duplicated code. - Add spl_boot_device() that returns the statically chosen boot device. Signed-off-by: Tom Rini <trini@ti.com>
| * SPL: Create arch/arm/lib/spl.c for board_init_f and jump_to_image_linuxTom Rini2012-09-27-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In SPL (CONFIG_SPL_FRAMEWORK) board_init_f must setup the stack pointer, clear the BSS and call board_init_r. We mark this as weak as some platforms may need to perform additional initalization at this point. We provide a gd that we know will be in a usable location, once the BSS has been cleared to help with this as well. Finally, we no longer call relocate_code so remove that from the armv7 version. Next, both board_init_f and jump_to_image_linux are going to be inherently arch-specific, so move these versions to arch/arm/lib/spl.c Signed-off-by: Tom Rini <trini@ti.com>
| * SPL: Move the omap SPL framework to common/splTom Rini2012-09-27-40/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a new flag, CONFIG_SPL_FRAMEWORK to opt into the common/spl SPL framework, enable on all of the previously using boards. We move the spl_ymodem.c portion to common/ and spl_mmc.c to drivers/mmc/. We leave the NAND one in-place as we plan to replace it later in this series. We use common/spl to avoid linker problems with respect to merging constant strings in objects. Otherwise all strings in common/ will be linked in and kept which grows SPL in size too much. Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: SPL: Start hooking in the current SPI SPL supportTom Rini2012-09-27-0/+3
| | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: SPL: Make spl_mmc.c more genericTom Rini2012-09-27-5/+5
| | | | | | | | | | | | | | | | Move the default omap/related-centric board_mmc_init to arch/arm/cpu/armv7/omap-common/boot-common.c and move the type defines to <asm/spl.h>. Also use mmc->read_bl_len rather than MMCSD_SECTOR_SIZE Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: SPL: Add <asm/spl.h> and <asm/arch/spl.h>Tom Rini2012-09-27-71/+196
| | | | | | | | | | | | | | Move the SPL prototypes from <asm/omap_common.h> into <asm/spl.h> and add <asm/arch/spl.h> for arch specific portions of CONFIG_SPL_FRAMEWORK. Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: SPL: Remove NAND_MODE_HW_ECC from spl_nand.cTom Rini2012-09-27-1/+0
| | | | | | | | | | | | | | This detection code doesn't (and can't) do anything currently, so remove. Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: SPL: Rename omap_boot_mode to spl_boot_mode()Tom Rini2012-09-27-1/+1
| | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: SPL: Rename omap_boot_device to spl_boot_deviceTom Rini2012-09-27-1/+1
| | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * omap-common: SPL: Add CONFIG_SPL_DISPLAY_PRINT / spl_display_print()Tom Rini2012-09-27-3/+1
| | | | | | | | | | | | | | | | Only omap4/5 currently have a meaningful set of display text and overo had been adding a function to display nothing. Change how this works to be opt-in and only turned on for omap4/5 now. Signed-off-by: Tom Rini <trini@ti.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-09-21-110/+289
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| * | ARM: Remove apollon boardMarek Vasut2012-09-18-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board is the only board that still sticks to OneNAND IPL. Remove this board, since we have SPL around for a while and OneNAND is well supported in the SPL framework. The board can be revived if necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Tom Rini <trini@ti.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2012-09-17-1/+2
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| | * | omap4 i2c: add support for i2c bus 4Koen Kooi2012-09-06-1/+2
| | | | | | | | | | | | | | | | Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
| * | | mmc: s5p_sdhci: fixed wrong function argumentJaehoon Chung2012-09-05-4/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | Useless code is removed, and get buswidth value. buswidth value will be used to choice the 4bit or 8bit. (Now used 4bit mode in sdhci.c by default) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungin.park@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-usbWolfgang Denk2012-09-02-0/+159
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-usb: MUSB driver: Timeout is never detected as the while loop does not end usb: fix ulpi_set_vbus prototype pxa25x: Add UDC registers definitions USB: Fix strict aliasing in ohci-hcd usb: Optimize USB storage read/write ehci: Optimize qTD allocations usb_stor_BBB_transport: Do not delay when not required usb_storage: Remove EHCI constraints usb_storage: Restore non-EHCI support ehci-hcd: Boost transfer speed ehci: cosmetic: Define used constants ehci: Fail for multi-transaction interrupt transfers arm:trats: Enable g_dnl composite USB gadget with embedded DFU function on TRATS arm:trats: Support for USB UDC driver at TRATS board. dfu:cmd: Support for DFU u-boot command dfu: MMC specific routines for DFU operation dfu: DFU backend implementation dfu:usb: DFU USB function (f_dfu) support for g_dnl composite gadget dfu:usb: Support for g_dnl composite download gadget. ehci: cosmetic: Define the number of qt_buffers Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * | pxa25x: Add UDC registers definitionsŁukasz Dałek2012-09-01-0/+159
| | | | | | | | | | | | | | | | Signed-off-by: Łukasz Dałek <luk0104@gmail.com>
* | | | Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2012-09-29-0/+2
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| * | | mx51evk: Add CONFIG_REVISION_TAGBenoît Thébaudeau2012-09-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. If this data is not present, the kernel misconfigures the TZIC, which results in the timer interrupt handler never being called, so the kernel deadlocks while calibrating its delay. Suggested-by: Greg Topmiller <Greg.Topmiller@jdsu.com> Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | | Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2012-09-21-91/+123
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| * | | MX6: drop binary constants from iomux headerStefano Babic2012-09-17-62/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Constants set with binary value (0b...) are not compiled from old toolchain when used by the clrsetbits_le32 macro. Replaces them with the corresponding hex value. The error reported (for example with the mx6qsabrelite board) is something like: mx6qsabrelite.c:369:1: error: invalid suffix "b101" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b10010" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b0000" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b10001" on integer constant Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | mx31: Define default SoC input clock frequenciesBenoît Thébaudeau2012-09-06-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX31 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Helmut Raiger <helmut.raiger@hale.at>
| * | | mx35: Define default SoC input clock frequenciesBenoît Thébaudeau2012-09-06-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX35 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | mx25: Define default SoC input clock frequenciesBenoît Thébaudeau2012-09-06-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX25 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Matthias Weisser <weisserm@arcor.de>
| * | | mx35: Fix clock dividersBenoît Thébaudeau2012-09-06-29/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock dividers that were used do not match at all the reference manual. They were either completely broken, or came from an early silicon revision incompatible with the current one. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | mx35: Add definitions for clock gate valuesBenoît Thébaudeau2012-09-06-0/+6
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | | | Tegra: Change Tegra20 to Tegra in common code, prep for T30Tom Warren2012-09-10-19/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate. Convert tegra20_ source file and function names to tegra_, also. Upcoming Tegra30 port will use common code/defines/names where possible. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* | | | tegra: nand: Add Tegra NAND driverJim Lin2012-09-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A device tree is used to configure the NAND, including memory timings and block/pages sizes. If this node is not present or is disabled, then NAND will not be initialized. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-12-28 17:37:18 +0000