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* ARM: tegra: use DT bindings for GPIO namingStephen Warren2016-05-31-227/+0
| | | | | | | | | | There are currently many places that define the list of all Tegra GPIOs; the DT binding header and custom Tegra-specific header file gpio.h. Fix the redundancy by replacing everything with the DT binding header file. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: video: Move LCD enums into the driverSimon Glass2016-02-16-22/+0
| | | | | | | | | There is no need to have these in a separate file as they are not referenced from anywhere else. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: video: Convert tegra20 LCD driver to driver modelSimon Glass2016-02-16-26/+0
| | | | | | | | | | | Move this driver over to use driver model. This involves rearranging the code somewhat. The effect is that everything is run from the probe() method. Boards which use this are fixed up, but only seaboard is tested. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: video: Merge the two config structures togetherSimon Glass2016-02-16-39/+0
| | | | | | | | | We have a structure for the display panel and another for the controller. There is some overlap between them. Merge them to simplify the driver. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: video: Merge the display driver into one fileSimon Glass2016-02-16-21/+0
| | | | | | | | | | | At present we have code in arch/arm and code in drivers/video. Move it all into drivers/video since it is a display driver and our current approach is to put all driver code in drivers/. Make a few functions static now that they are not used outside the file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Implement clk_mThierry Reding2015-09-16-0/+1
| | | | | | | | | | On currently supported SoCs, clk_m always runs at the same frequency as the oscillator input. However newer SoC generations such as Tegra210 no longer have that restriction. Prepare for that by separating clk_m from the oscillator clock and allow SoC code to override the clk_m rate. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Move display controller header into commonSimon Glass2015-05-13-530/+1
| | | | | | | Allow this to be used by other Tegra SoCs. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Move the pwm into tegra-commonSimon Glass2015-05-13-50/+4
| | | | | | | | This is needed for tegra124 also, so make it common and add a header file for tegra124. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: ARM720t: remove empty asm/arch/hardware.hMasahiro Yamada2015-04-23-13/+0
| | | | | | | | | | arch/arm/cpu/arm720t/start.S includes <asm/arch/hardware.h>, but the hardware.h headers of ARM720T boards are all empty. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pinmux: account for different drivegroup base registersStephen Warren2015-03-04-0/+1
| | | | | | | | Tegra210 starts its drive group registers at a different offset from the APB MISC register block that other SoCs. Update the code to handle this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* dm: tegra: video: Remove use of fdtdec GPIO supportSimon Glass2015-01-29-4/+5
| | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* ARM: tegra: Implement powergate supportThierry Reding2014-12-18-0/+6
| | | | | | | | | Implement the powergate API that allows various power partitions to be power up and down. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Provide PCIEXCLK reset IDThierry Reding2014-12-18-1/+1
| | | | | | | | | | | | | This reset is required for PCIe and the corresponding ID therefore needs to be defined. The enumeration value for this was properly defined on some SoCs but not on others. Similarly, some contained it in the mapping of peripheral IDs to clock IDs, other didn't. This patch defines it consistently for all supported SoC generations. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Implement tegra_plle_enable()Thierry Reding2014-12-18-0/+2
| | | | | | | | | | | This function is required by PCIe and SATA. This patch implements it on Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because it doesn't support PCIe or SATA. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2014-10-23-0/+37
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| * ARM: tegra: Use mem size from MC in combination with get_ram_size()Marcel Ziswiler2014-10-22-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On popular request this now completes the Warren's work started for TK1: aeb3fcb35956461077804720b8a252d50758d7e0 ARM: tegra: Use mem size from MC rather than ODMDATA In addition to the move of using the Tegra memory controller (MC) register rather than ODMDATA for T20, T30 and T114 as well it further uses the generic get_ram_size() function (see "common/memsize.c") <supposed to be used in each and every U-Boot port>TM. Added benefit is that it should <catch 99% of hardware related (i. e. reliably reproducible) memory errors> as well. Thoroughly tested on the various Toradex line of Tegra modules available which unfortunately does not include T114 and T124 (yet at least) plus on the Jetson TK1. Based-on-work-by: Stephen Warren <swarren@nvidia.com> Based-on-work-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | dm: tegra: spi: Convert to driver modelSimon Glass2014-10-22-82/+0
|/ | | | | | | | | | | | | | This converts the Tegra SPI drivers to use driver model. This is tested on: - Tegra20 - trimslice - Tegra30 - beaver - Tegra124 - dalmore (not tested on Tegra124) Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* tegra: kconfig: move board select menu and common settingsMasahiro Yamada2014-08-30-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Becuase the board select menu in arch/arm/Kconfig is too big, move the Tegra board select menu to tegra/Kconfig. Insert the Tegra SoC select menu between the arch select and the board select. Architecture select |-- Tegra Platform (Tegra) |- Tegra SoC select (Tegra20 / 30 / 114 / 124) |- Board select Consolidate also common settings (CONFIG_SYS_CPU="armv7" and CONFIG_SYS_SOC="tegra*") and always "select" CONFIG_SPL as follows: config TEGRA bool select SPL Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com>
* spl: consolidate arch/arm/include/asm/arch-*/spl.hMasahiro Yamada2014-06-06-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch/arm/include/asm/spl.h requires all SoCs to have arch/arm/include/asm/arch-*/spl.h. But many of them just define BOOT_DEVICE_* macros. Those macros are used in the "switch (boot_device) { ... }" statement in common/spl/spl.c. So they should not be archtecture specific, but be described as a simpile enumeration. This commit merges most of arch/arm/include/asm/arch-*/spl.h into arch/arm/include/asm/spl.h. With a little more effort, arch-zynq/spl.h and arch-socfpga/spl.h will be merged, while I am not sure about OMAP and Exynos. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com> CC: Stefano Babic <sbabic@denx.de> CC: Minkyu Kang <mk7.kang@samsung.com> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Bo Shen <voice.shen@atmel.com> [on sama5d3xek board for at91 part] Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stefano Babic <sbabic@denx.de> [applying Tim's i.MX6 patches] Acked-by: Tom Rini <trini@ti.com>
* ARM: tegra: allow pinmux mux option not to be set by init tablesStephen Warren2014-05-13-0/+1
| | | | | | | | | | | | | Define enum PMUX_FUNC_DEFAULT, which indicates that a table entry passed to pinmux_config_pingrp()/pinmux_config_pingrp_table() shouldn't change the mux option in HW. For pins that will be used as GPIOs, the mux option is irrelevant, so we simply don't want to define any mux option in the pinmux initialization table. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pack pinmux data tables tighterStephen Warren2014-04-17-4/+4
| | | | | | | | | | | | | | | | Use smaller fields in the Tegra pinmux structures in order to pack the data tables into a smaller space. This saves around 1-3KB for the SPL and around 3-8KB for the main build of U-Boot, depending on the board, which SoC it uses, and how many pinmux table entries there are. In order to pack PMUX_FUNC_* into a smaller space, don't hard-code the values of PMUX_FUNC_RSVD* to values which require 16 bits to store them, but instead let their values be assigned automatically, so they end up fitting into 8 bits. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* usb: tegra: combine header fileStefan Agner2014-04-17-160/+0
| | | | | | | | | | | Combine the Tegra USB header file into one header file for all SoCs. Use ifdef to account for the difference, especially Tegra20 is quite different from newer SoCs. This avoids duplication, mainly for Tegra30 and newer devices. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
* usb: tegra: fix PHY configurationStefan Agner2014-04-17-1/+6
| | | | | | | | | | | | | | | | On Tegra30 and later, the PTS (parallel transceiver select) and STS (serial transceiver select) are part of the HOSTPC1_DEVLC_0 register rather than PORTSC1_0 register. Since the reset configuration usually matches the intended configuration, this error did not show up on Tegra30 devices. Also use the slightly different bit fields of first USB, (USBD) on Tegra20 and move those definitions to the Tegra20 specific header file. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Tegra20 pinmux cleanupStephen Warren2014-04-17-135/+131
| | | | | | | | | | | | | | This renames all the Tegra20 pinmux pins and functions so they have a prefix which matches the type name. The entries in tegra20_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pinmux naming consistency fixesStephen Warren2014-04-17-1/+1
| | | | | | | | | | | | | | | Clean up the naming of pinmux-related objects: * Refer to drive groups rather than pad groups to match the Linux kernel. * Ensure all pinmux API types are prefixed with pmux_, values (defines) are prefixed with PMUX_, and functions prefixed with pinmux_. * Modify a few type names to make their content clearer. * Minimal changes to SoC-specific .h/.c files are made so the code still compiles. A separate per-SoC change will be made immediately following, in order to keep individual patch size down. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pinctrl: remove duplicationStephen Warren2014-04-17-81/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Much of arch/arm/cpu/tegra*-common/pinmux.c is identical. Remove the duplication by creating pinmux-common.c for all the identical code. This leaves: * arch/arm/include/asm/arch-tegra*/pinmux.h defining only the names of the various pins/pin groups, drive groups, and mux functions. * arch/arm/cpu/tegra*-common/pinmux.c containing only the lookup table stating which pin groups support which mux functions. The code in pinmux-common.c is semantically identical to that in the various original pinmux.c, but had some consistency and cleanup fixes applied during migration. I removed the definition of struct pmux_tri_ctlr, since this is different between SoCs (especially Tegra20 vs all others), and it's much simpler to deal with this via the new REG/MUX_REG/... defines. spl.c, warmboot.c, and warmboot_avp.c needed updates due to this, since they previously hijacked this struct to encode the location of some non-pinmux registers. Now, that code simply calculates these register addresses directly using simple and obvious math. I like this method better irrespective of the pinmux code cleanup anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: use apb_misc.h in more placesStephen Warren2014-04-17-20/+0
| | | | | | | | | | | | | | | | | Tegra's "APB misc" register region contains various miscellaneous registers and the Tegra pinmux registers. Some code that touches the misc registers currently uses struct pmux_tri_ctlr, which is intended to be a definition of pinmux registers, rather than struct apb_misc_pp_ctrl, which is intended to be a definition of the miscellaneous registers. Convert all such code to use struct apb_misc_pp_ctrl, since struct pmux_tri_ctlr goes away in the next patch. This requires adding a missing field definition to struct apb_misc_pp_ctrl, and moving the header into a more common location. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20Stephen Warren2014-04-17-10/+7
| | | | | | | | | | | | | | | | | For consistency with other SoCs, modify Tegra20's enum pmux_func to: * Remove PMUX_FUNC values that aren't real * Use the same PMUX_FUNC_RSVD[1-4] values, and ensure (RSVD1 & 3)==0; this will be assumed by pinmux_set_func() in a future patch. Unfortunately, PMUX_FUNC_RSVD is still used in the pin macros. Use a private define inside the driver to prevent this from causing compilaton errors. This will be cleaned up when the pin tables are re-written in a later patch in this series. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pinctrl: remove vddioStephen Warren2014-04-17-15/+0
| | | | | | | | | | This field isn't used anywhere, so remove it. Note that PIN() macros are left unchanged for now, to avoid many diffs to them; later commits will completely rewrite them just one time. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pinctrl: remove func_safeStephen Warren2014-04-17-1/+0
| | | | | | | | | | This field isn't used anywhere, so remove it. Note that PIN() macros are left unchanged for now, to avoid many diffs to them; later commits will completely rewrite them just one time. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: move CONFIG_TEGRAnnStephen Warren2014-03-05-0/+2
| | | | | | | | | | <asm/arch-tegra/tegra.h> needs to use CONFIG_TEGRA* to conditionalize some definitions, since some modules moved between generations. Move the definition of CONFIG_TEGRAnn to a header that's included earlier, so that it's set by the time tegra.h needs to use it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-284/+17
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* ARM: Tegra: USB: EHCI: Add support for Tegra30/Tegra114Jim Lin2013-07-11-0/+155
| | | | | | | | | | Tegra30 and Tegra114 are compatible except PLL parameters. Tested on Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* spi: add common fdt SPI driver interfaceAllen Martin2013-03-25-0/+22
| | | | | | | | | | | Add a common interface to fdt based SPI drivers. Each driver is represented by a table entry in fdt_spi_drivers[]. If there are multiple SPI drivers in the table, the first driver to return success from spi_init() will be registered as the SPI driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra: spi: pull register structs out of headersAllen Martin2013-03-25-99/+0
| | | | | | | | | | Move register structs from headers into .c files and use common name. This is in preparation of making common fdt front end for SPI drivers. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra: spi: rename tegra SPI driversAllen Martin2013-03-25-0/+159
| | | | | | | | | Rename tegra SPI drivers to tegra20_flash and tegra20_slink in preparation for commonization and addition of tegra114_spi. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra: remove support for UART SPI switchAllen Martin2013-03-25-46/+0
| | | | | | | | | | This feature was only used for tegra20 seaboard that had a pinmux conflict on the SPI pins. These boards were never manufactured, so remove this support to clean up SPI driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra: usb: move implementation into right directoryLucas Stach2013-03-14-269/+0
| | | | | | | | | | | | | | | | This moves the Tegra USB implementation into the drivers/usb/host directory. Note that this merges the old /arch/arm/cpu/armv7/tegra20/usb.c file into ehci-tegra.c. No code changes, just moving stuff around. v2: While at it also move some defines and the usb.h header file to make usb driver usable for Tegra30. NOTE: A lot more work is required to properly init the PHYs and PLL_U on Tegra30, this is just to make porting easier and it does no harm here. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: various small cleanupsLucas Stach2013-03-14-3/+0
| | | | | | | | | Remove unneeded headers, function prototype and stale comment, that doesn't match the actual codebase anymore. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: rename FUNCMUX_UART2_UARTBStephen Warren2013-02-11-1/+1
| | | | | | | | | FUNCMUX_ defines should be named after the pin groups they affect, not after the module they're muxing onto those pin groups. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.cTom Warren2013-02-11-0/+10
| | | | | | | | | This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: remove IRDA pinmux synonymAllen Martin2013-01-16-2/+1
| | | | | | | | | IRDA is a synonym for UARTB in tegra pinmux, remove all usage of this synonym and replace with UARTB to disambiguate. Signed-off-by: Allen Martin <amartin@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Tegra30: Add arch-tegra30 include filesTom Warren2013-01-16-33/+10
| | | | | | | | | | | | Common Tegra files are in arch-tegra, shared between T20 and T30. Tegra30-specific headers are in arch-tegra30. Note that some of these will be filled in as more T30 support is added (drivers, WB/LP0 support, etc.). A couple of Tegra20 files were changed to support common headers in arch-tegra, also. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* tegra: Add SOC support for display/lcdWei Ni2012-11-19-0/+697
| | | | | | | | | | | | | | Add support for the LCD peripheral at the Tegra2 SOC level. A separate LCD driver will use this functionality to configure the display. Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Mayuresh Kulkarni: - changes to remove bitfields and clean up for submission Signed-off-by: Simon Glass <sjg@chromium.org> Simon Glass: - simplify code, move clock control into here, clean-up Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add support for PWMSimon Glass2012-11-19-0/+75
| | | | | | | | The pulse width/frequency modulation peripheral supports generating a repeating pulse. It is useful for controlling LCD brightness. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Use const for pinmux_config_pingroup/table()Simon Glass2012-11-19-2/+2
| | | | | | | | | These two functions don't actually modify their arguments so add a const keyword. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: move to common SPL frameworkAllen Martin2012-10-29-0/+28
| | | | | | | | | | | | | | | | Change tegra SPL to use common SPL framework. Any tegra specific initialization is now done in spl_board_init() instead of board_init_f()/board_init_r(). Only one SPL boot target is supported on tegra, which is boot to RAM image. jump_to_image_no_args() must be overridden on tegra so the host CPU can be initialized. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Tested-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: add funcmux entry for NAND attached to KBCLucas Stach2012-10-15-0/+1
| | | | | | | | Secondary config for the Flash attachment. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: add clock_set_pllout functionLucas Stach2012-10-15-0/+7
| | | | | | | | | | | Common practice on Tegra 2 boards is to use the pllp_out4 FO to generate the ULPI reference clock. For this to work we have to override the default hardware generated output divider. This function adds a clean way to do so. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: complete periph_id enumLucas Stach2012-10-15-0/+6
| | | | | | | | | | | | Most Tegra boards output the ULPI reference clock on pad DEV2. Complete the periph_id enum so that we are able to enable this clock output circuit. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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