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* ARM: Migrate errata to KconfigTom Rini2017-03-09-6/+0
| | | | | | | | | This moves all of the current ARM errata from various header files and in to Kconfig. This allows for a minor amount of cleanup as we had some instances where both a general common header file was enabling errata as well as the board config. We now just select these once at the higher level in Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
* board: freescale: ls1012a: Enable secure DDR on LS1012A platformsPrabhakar Kushwaha2017-02-03-0/+3
| | | | | | | | | | | PPA binary needs to be relocated on secure DDR, hence marking out a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag is set Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043a: fixup GIC offset for ls1043a rev1Wenbin Song2017-01-18-0/+22
| | | | | | | | | | | | | | | | | | | | | | | The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/fsl_lsch2: Add the OCRAM initializationHou Zhiqiang2017-01-18-0/+3
| | | | | | | | | | | | | | Clear the content to zero and the ECC error bit of OCRAM1/2. The OCRAM must be initialized to ZERO by the unit of 8-Byte before accessing it, or else it will generate ECC error. And the IBR has accessed the OCRAM before this initialization, so the ECC error status bit should to be cleared. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ARMv8/fsl-layerscape: Correct the OCRAM sizeHou Zhiqiang2017-01-18-3/+5
| | | | | | | | | The real size of OCRAM is 128KiB, so correct the size of OCRAM. And OCRAM reserved 2MiB space, then add a new macro to describe it, which is used for MMU setup. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to KconfigYork Sun2017-01-04-20/+0
| | | | | | Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
* fsl_ddr: Move DDR config options to driver KconfigYork Sun2017-01-04-2/+2
| | | | | | | | | Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
* crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to KconfigYork Sun2017-01-04-4/+0
| | | | | | | Use Kconfig option to set little- or big-endian access to secure boot and trust architecture. Signed-off-by: York Sun <york.sun@nxp.com>
* crypto: Move SYS_FSL_SEC_COMPAT into driver KconfigYork Sun2017-01-04-2/+0
| | | | | | | Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC and ARM SoCs, move it to Kconfig under the driver. Signed-off-by: York Sun <york.sun@nxp.com>
* script: remove CONFIG_SYS_CCSRBAR_DEFAULT from white listYork Sun2016-12-02-1/+0
| | | | | | | Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT in Kconfig. Drop this macro for LSCH2 and remove from white list. Signed-off-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Add NXP LS2088A SoC supportPriyanka Jain2016-11-22-0/+1
| | | | | | | | | | | | The QorIQ LS2088A SoC is built on layerscape architecture. It is similar to LS2080A SoC with some differences like 1)Timer controller offset is different 2)It has A72 cores 3)It supports TZASC module Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Move DDR config options to KconfigYork Sun2016-10-06-14/+0
| | | | | | | | Move DDR3, DDR4 and realted options to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Move SYS_FSL_SRDS_* and SYS_HAS_SERDES to KconfigYork Sun2016-10-06-5/+0
| | | | | | | Move these options to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Move FSL_HAS_DP_DDR and NUM_DDR_CONTROLLERS to KconfigYork Sun2016-10-06-3/+0
| | | | | | | | Move this option to Kconfig and clean up existing uses. NUM_DDR_CONTROLLERS is also used by PowerPC SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Move SYS_FSL_IFC_BANK_COUNT to KconfigYork Sun2016-10-06-3/+0
| | | | | | | | Move this option to Kconfig and clean up existing uses. This option is also used by PowerPC SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Move MAX_CPUS to KconfigYork Sun2016-10-06-4/+0
| | | | | | | | Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This option is used by Freescale Layerscape SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SYS_FSL_ERRATUM_A010315 to Kconfig optionYork Sun2016-09-26-1/+0
| | | | | | | Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
* armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021AYork Sun2016-09-26-4/+2
| | | | | | | | | Move this config to Kconfig option and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Calvin Johnson <calvin.johnson@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* armv8: ls1046a: Convert CONFIG_LS1046A to Kconfig option ARCH_LS1046AYork Sun2016-09-26-1/+2
| | | | | | | | | Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Mingkai Hu <mingkai.hu@nxp.com> CC: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* armv8: ls1046a: Enable DDR erratum for ls1046aShengzhou Liu2016-09-14-0/+6
| | | | | | | | | Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803, ERRATUM_A009942, ERRATUM_A010165 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for standalone appShaohui Xie2016-09-14-0/+2
| | | | | | | | The CONFIG_STANDALONE_LOAD_ADDR is set to 0x80300000 by default. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu2016-09-14-1/+3
| | | | | | | | | | | | | | This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl-layerscape: Add workaround for PCIe erratum A010315Hou Zhiqiang2016-09-14-0/+2
| | | | | | | | | | As the access to serders protocol unselected PCIe controller will hang. So disable the R/W permission to unselected PCIe controller including its CCSR, IO space and memory space according to the serders protocol field of RCW. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ARM: Move SYS_CACHELINE_SIZE over to KconfigTom Rini2016-08-26-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: Paul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: "Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Chin Liang See <clsee@altera.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Paul Kocialkowski <contact@paulk.fr>
* armv8: fsl_lsch2: Add LS1046A SoC supportMingkai Hu2016-07-26-0/+27
| | | | | | | | | | | The LS1046A processor is built on the QorIQ LS series architecture combining four ARM A72 processor cores with DPAA 1.0 support. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Consolidate the LSCH2 common definesQianyu Gong2016-07-26-39/+20
| | | | | | | | | Both LS1012A and LS1043A belong to FSL_LSCH2 and share some common configurations. So put the common define under FSL_LSCH2 to increase readability. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Add support of QorIQ LS1012A SoCPrabhakar Kushwaha2016-06-03-0/+29
| | | | | | | | | | | | | | | | | | | | | The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* driver/ddr/fsl: Add workaround for erratum A-010165Shengzhou Liu2016-05-18-0/+1
| | | | | | | | | During DDR-2133 operation, the transmit data eye margins determined during the memory controller initialization may be sub-optimal, set DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arch/arm, arch/powerpc: add # of SEC engines on the SOCAlex Porosanu2016-05-18-0/+2
| | | | | | | | | | Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu2016-05-17-0/+1
| | | | | | | | The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043: Add workaround for DDR erratum A-008850Shengzhou Liu2016-05-17-0/+1
| | | | | | | | | Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: LS2080A: Consolidate LS2080A and LS2085AYork Sun2016-04-06-7/+2
| | | | | | | | | | | | LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* armv8: ls2080: Add config for endianess of CCSR GURSaksham Jain2016-03-29-0/+3
| | | | | | | | | | The GUR (DCFG) registers in CCSR space are in little endian format. Define a config CONFIG_SYS_FSL_CCSR_GUR_LE in arch/arm/include/asm/arch-fsl-layerscape/config.h Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-lsch3: Add new header for secure bootSaksham Jain2016-03-29-1/+2
| | | | | | | | | | | | | | For secure boot, a header is used to identify key table, signature and image address. A new header structure is added for lsch3. Currently key extension (IE) feature is not supported. Single key feature is not supported. Keys must be in table format. Hence, SRK (key table) must be present. Max key number has increase from 4 to 8. The 8th key is irrevocable. A new barker Code is used. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080: Add configs for SEC, SecMon, SRK and DCFGSaksham Jain2016-03-29-0/+10
| | | | | | | | | | | Add configs for various IPs used during secure boot. Add address and endianness for SEC and Security Monitor. SRK are fuses in SFP (fuses for public key's hash). These are stored in little endian format. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080: Add SFP Configs for LS2080Saksham Jain2016-03-29-0/+4
| | | | | | | | | In LS2080, SFP has version 3.4. It is in little endian. The base address is 0x01e80200. SFP is used in Secure Boot to read fuses. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* driver/ddr/fsl: Add workaround for erratum A-009803Shengzhou Liu2016-03-21-0/+1
| | | | | | | | | During initial DDR training, false parity errors may be detected. This patch adds workaround to fix the erratum. Tested on LS2085QDS and LS2080RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: lsch3: Enable WUO config for RNI-20 nodePrabhakar Kushwaha2016-03-21-0/+2
| | | | | | | | | | Enable wuo config to accelerate coherent ordered writes for LS2080A and LS2085A. WRIOP IP is connected to RNI-20 Node. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043a: Implement workaround for erratum A009660Mingkai Hu2016-02-24-0/+1
| | | | | | | | | Memory controller performance is not optimal with default internal target queue register value, write required value for optimal DDR performance. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043a: enable workaround for errarum A009942Shengzhou Liu2016-02-24-0/+1
| | | | | | | DDR erratum A-009942 applies to LS1043A. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm8: ls2080: Move the core errata defines out of board specific fileAshish kumar2016-02-01-0/+2
| | | | | | | Valid for core A57 Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080a: Implement workaround for core errata 829520, 833471Ashish kumar2016-02-01-0/+4
| | | | | | | | | | | | | 829520: Code bounded by indirect conditional branch might corrupt instruction stream. Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect Predictor. 833471: VMSR FPSCR functional failure or deadlock. Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* driver/ddr/fsl: Add workaround for A009663Shengzhou Liu2016-01-25-0/+3
| | | | | | | | | | | | Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl/ddr: Add workaround for ERRATUM_A009942Shengzhou Liu2016-01-25-0/+1
| | | | | | | | | | | | During the receive data training, the DDRC may complete on a non-optimal setting that could lead to data corruption or initialization failure. Workaround: before setting MEM_EN, set DEBUG_29 register with specific value for different data rates. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043a: Implement workaround for PEX erratum A009929Mingkai Hu2015-12-17-0/+1
| | | | | | | | | Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043ardb: add SECURE BOOT target for NORAneesh Bansal2015-12-15-2/+2
| | | | | | | | | | LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8: fsl-layerscape: Make DDR non secure in MMU tablesYork Sun2015-12-15-0/+6
| | | | | | | | | | | | | | | | | | | DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/ls1043ardb: Add support for >2GB memoryShaohui Xie2015-12-13-2/+2
| | | | | | | | This patch also expose the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8: ls2085a: Add workaround of errata A009635Prabhakar Kushwaha2015-11-30-0/+9
| | | | | | | | | | | | | If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3York Sun2015-11-30-0/+7
| | | | | | | | Freescale LSCH3 platforms use two DDR controlers interleaving mode out of reset. It can be configured to disable one controller. To support this operation, the driver needs to detect and skip the disabled controller. Signed-off-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-01 14:26:40 +0000