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| * | | | ARM: UniPhier: display boot swap pin status by pinmon commandMasahiro Yamada2014-12-30-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This information would be useful enough. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: UniPhier: add dump command of DDR PHY parametersMasahiro Yamada2014-12-30-0/+237
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a dump command of DDR PHY parameters of UniPhier SoC family. It might not be used very often for the regular operation but it would be useful when something goes wrong with DDR memories. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: UniPhier: add DDR PHY training codeMasahiro Yamada2014-12-30-3/+414
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | This training code provides run-time adjustment of DDR PHY parameters for stable DDR operation. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2014-12-30-0/+6
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| * | | arm: exynos: clock: support SPLL as mmc source clock for exynos5420Joonyoung Shim2014-12-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMC of exynos5420 can select SPLL as source clock, so add to support SPLL in exynos5420_get_mmc_clk(). It was tested on Odroid-XU3 board. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Odroid-XU3: Add support for Odroid-XU3Hyungwon Hwang2014-12-22-0/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for Odroid-XU3. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | bcm281xx: add support for "USB OTG clock"Steve Rae2014-12-29-0/+49
|/ / | | | | | | | | | | | | | | enable this clock with the following: clk_usb_otg_enable((void *)HSOTG_BASE_ADDR) Signed-off-by: Steve Rae <srae@broadcom.com> Reviewed-by: Felipe Balbi <balbi@ti.com>
* | ARM: UniPhier: remove unnecessary ifdef conditionalMasahiro Yamada2014-12-18-4/+0
|/ | | | | | init_page_table is only set on SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-12-16-6/+4
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| * socfpga: correctly increment freeze_controller_base addressDinh Nguyen2014-12-06-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | Correctly increment the base address of the freeze controller. And since SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * arm: socfpga: Use only one clrbits_le32 call to deassert SPI reset bitsStefan Roese2014-12-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | As suggested by Pavel, lets combine the two calls into one. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* | Merge git://git.denx.de/u-boot-dmTom Rini2014-12-11-5/+26
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| * | dm: i2c: tegra: Convert to driver modelSimon Glass2014-12-11-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts all Tegra boards over to use driver model for I2C. The driver is adjusted to use driver model and the following obsolete CONFIGs are removed: - CONFIG_SYS_I2C_INIT_BOARD - CONFIG_I2C_MULTI_BUS - CONFIG_SYS_MAX_I2C_BUS - CONFIG_SYS_I2C_SPEED - CONFIG_SYS_I2C This has been tested on: - trimslice (no I2C) - beaver - Jetson-TK1 It has not been tested on Tegra 114 as I don't have that board. Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | ARM: tegra: Add support for nyan-big boardAllen Martin2014-12-11-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC. This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA Tegra K1, 2GB). The display is not currently supported, so it should boot on other nyan-based Chromebooks also, but only the device tree for nyan-big is provided here. The device tree file is from Linux but with features removed which are unlikely to be supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> (rebase, change to 'nyan-big', fix pinmux that resets nyan-big)
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-12-11-3/+203
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| * | ls1021a: adding a secondary core boot address and kick functionsXiubo Li2014-12-11-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the LS1021A specific manner. Define the board specific smp_kick_all_cpus() functioin to boot a secondary core. Here the BRR contains control bits for enabling boot for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to be released for booting or to remain in boot holdoff. All other cores remain in boot holdoff until their corresponding bit is set. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.Xiubo Li2014-12-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some SoCs, the system clock frequency may not equal to the ARCH Timer's frequency. This patch uses the CONFIG_TIMER_CLK_FREQ instead of CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer macor could be set separately and without interfering each other. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ARM: HYP/non-sec: add the pen address BE mode support.Xiubo Li2014-12-11-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some SoCs, the pen address register maybe in BE mode and the CPUs are in LE mode. This patch adds BE mode support for smp pen address. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Add SD boot support for LS1021AQDS boardAlison Wang2014-12-11-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SD boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: spl: Add I2C linker list in generic .ldsAlison Wang2014-12-11-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On LS1, DDR is initialized by reading SPD through I2C interface in SPL code. For I2C, ll_entry_count() is called, and it returns the number of elements of a linker-generated array placed into subsection of .u_boot_list section specified by _list argument. So add I2C linker list in the generic .lds to fix the issue about using I2C in SPL. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: clear EPU registers for deep sleepchenhui zhao2014-12-11-0/+142
| | | | | | | | | | | | | | | | | | | | | | | | After wakeup from deep sleep, Clear EPU registers as early as possible to prevent from possible issue. It's also safe to clear at normal boot. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: fixed a bus frequency setting errorTang Yuantian2014-12-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The bus frequency in SOC node should be clock frequency of platform. That is not true if it is devided by 2. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-12-10-11/+12
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| * | | arm: vf610: improve evaluation of reset sourceStefan Agner2014-12-01-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve the evaluation of the reset source. Bit description according to latest reference manual rev. 7. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | | arm: mx6: Change defines ENET_xxMHz to ENET_xxMHZ (no CamelCase)Stefan Roese2014-12-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As checkpatch complaines about these camel-case defines, lets change them to only use upper-case characters. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | | stv0991: enable ethernet supportVikas Manocha2014-12-09-0/+28
| | | | | | | | | | | | | | | | Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | | | stv0991: Add basic stv0991 architecture supportVikas Manocha2014-12-09-0/+237
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | stv0991 architecture support added. It contains the support for following blocks - Timer - uart Signed-off-by: Vikas Manocha <vikas.manocha@st.com> [trini: Add arch/arm/cpu/armv7/Makefile hunk] Signed-off-by: Tom Rini <trini@ti.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2014-12-08-14/+33
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| * | | arm: am33xx: Handle NAND+I2C boot-device the same way as NANDStefan Roese2014-12-04-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Re-map NAND&I2C boot-device to the "normal" NAND boot-device. Otherwise the SPL boot IF can't handle this device correctly. Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens Draco leads to this boot-device passed to SPL from the BootROM. With this change, Draco boots just fine into main U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Samuel Egli <samuel.egli@siemens.com>
| * | | beagle_x15: add board support for Beagle x15Felipe Balbi2014-12-04-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BeagleBoard-X15 is the next generation Open Source Hardware BeagleBoard based on TI's AM5728 SoC featuring dual core 1.5GHZ A15 processor. The platform features 2GB DDR3L (w/dual 32bit busses), eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60), separate LCD port, video In port, 4GB eMMC, uSD, Analog audio in/out, dual 1G Ethernet. For more information, refer to: http://www.elinux.org/Beagleboard:BeagleBoard-X15 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | arm: omap: add support for am57xx devicesFelipe Balbi2014-12-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | just add a few ifdefs around because this device is very similar to dra7xxx. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | arm: omap5: sdram: mark emif_get_ext_phy_ctrl_const_regs __weakFelipe Balbi2014-12-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this will allow for boards to overwrite those in case memory setup is different. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | arm: omap5: make hw_init_data weakFelipe Balbi2014-12-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this way we can let boards overwrite based on what they need. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | arm: omap-common: emif: allow to map memory without interleavingFelipe Balbi2014-12-04-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we want to have two sections, one on each EMIF, without interleaving, current code wouldn't enable emif2. Fix that problem. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | arm: dra7xx: prcm: add missing registersFelipe Balbi2014-12-04-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | some boards might want to use USB1 for host, without fiddling those registers it'll be impossible. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | arm: omap5: tps659038: rename regulator definesFelipe Balbi2014-12-04-5/+5
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | Those regulators don't have any coupling with what they supply, so remove the suffixes in order to not confuse anybody. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | ARM: UniPhier: detect the number of flash banks at run-timeMasahiro Yamada2014-12-09-40/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some UniPhier boards are equipped with an expansion slot that some optional SRAM/NOR-flash cards can be attached to. So, run-time detection of the number of flash banks would be more user-friendly. Until this commit, UniPhier boards have achieved this by (ab)using board_flash_wp_on() because the boot failed if flash_size got zero. Fortunately, this problem was solved by commit 70879a92561a (flash: do not fail even if flash_size is zero). Now it is possible to throw away such a tricky workaround. This commit also enables CONFIG_SYS_MAX_FLASH_BANKS_DETECT for further refactoring. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | ARM: UniPhier: extend register area of init page table for PH1-sLD3Masahiro Yamada2014-12-09-1/+6
| | | | | | | | | | | | | | | | | | | | | 0x20000000-0x2fffffff: assigned to ARM mpcore (sLD3 only) 0xf0000000-0xffffffff: assigned to Denali NAND controller (sLD3 only) Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | ARM: UniPhier: merge UniPhier config headers into a single fileMasahiro Yamada2014-12-08-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | Some configurations have been moved to Kconfig and the difference among the config headers of UniPhier SoC variants is getting smaller and smaller. Now is a good time to merge them into a single file. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | ARM: UniPhier: move support card select to KconfigMasahiro Yamada2014-12-08-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | There are two kinds of expansion boards which are often used for the UniPhier platform and they are only exclusively selectable. It can be better described by the "choice" menu of Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | ARM: UniPhier: move CONFIG_UNIPHIER_SMP to KconfigMasahiro Yamada2014-12-08-0/+4
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | ARM: UniPhier: use boot_is_swapped() macro for readabilityMasahiro Yamada2014-12-08-10/+10
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | ARM: UniPhier: remove Denali NAND controller fixup codeMasahiro Yamada2014-12-07-38/+0
|/ / | | | | | | | | | | | | This ugly work-around code is unnecessary since commit f09eb52b3ffc (mtd: denali: set some registers after nand_scan_ident()). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | usb: UniPhier: support OF configurationMasahiro Yamada2014-11-28-3/+0
| | | | | | | | | | | | | | | | | | If CONFIG_OF_CONTROL is defined, search device tree nodes that are compatible with "panasonic,uniphier-ehci" and take the base address from their "reg" property. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Marek Vasut <marex@denx.de>
* | ARM: UniPhier: do not compile platform data when CONFIG_OF_CONTROL=yMasahiro Yamada2014-11-28-3/+3
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-samsungTom Rini2014-11-26-14/+82
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| * | arm: odroid: enable/disable usb host phy for exynos4412Suriyan Ramasami2014-11-17-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | Enable/disable the usb host phy on the odroid U/X2 boards which are based on the Exynos4412 SOC. Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Peach-Pi: Use the enhanced usb_copy() prototypeVadim Bendebury2014-11-17-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos5800 IROM has a different, from 5250 and 5420, prototype of the usb_copy() function. Luckily the earlier version did not expect any arguments, which means the same code could be used with old and new SoCs, the old ones just ignoring the arguments. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos5: ddr3: Choose between single or double channel configAkshay Saraswat2014-11-17-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a 4G configuration and choose it based on the number of banks declared in config file. A board with 4 SDRAM banks declared (as per CONFIG_NR_DRAM_BANKS) will end up with the 2G confiuration. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | DMC: Exynos5: Enable update mode for DREX controllerAlim Akhtar2014-11-17-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per Exynos5800 UM ver 0.00 section 17.13.2.1 CONCONTROL register bit 3 [update_mode], Exynos5800 does not support the PHY initiated update. And it is recommanded to set this field to 1'b1 during initialization. This patch sets this bit. Applying MC-initiated mode makes DDL tracking ON, that helps in compensate MIF voltage variation. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
generated by cgit v1.1 at 2024-10-20 19:18:40 +0000