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| * | EXYNOS5: DWMMC: Initialise the local variable to avoid unwanted results.Amar2013-06-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch initialises the local variable 'shift' to zero. The uninitialised local variable 'shift' had garbage value and was resulting in unwnated results in the functions exynos5_get_mmc_clk() and exynos4_get_mmc_clk(). Signed-off-by: Amar <amarendra.xt@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | exynos: update tzpc to make it common for exynos4 and exynos5Inderpal Singh2013-06-04-7/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This requires that cpu_is_exynos4/5 should be made available before tzpc_init. Hence this patch also makes necessary changes to have cpu_info in spl and invokes arch_cpu_init before tzpc_init in low_level_init.S for smdk5250. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Acked-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | exynos: move tzpc_init to armv7/exynosInderpal Singh2013-06-04-1/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tzpc_init is common for all exynos5 boards, hence move it to armv7/exynos so that all other boards can use it. Also update the smdk5250 Makefile and config file. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Acked-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos5: clock: Update the equation to calculate PLL output frequencyAkshay Saraswat2013-05-21-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the latest exynos5 user manual, the equation for calculating PLL output was changed to FOUT= MDIV x FIN/(PDIV x 2^SDIV) earlier it was FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1)) So updating the clock code accordingly. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | arm: pxa: config option for PXA270 turbo modeSergey Yanovich2013-06-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | PXA270 CPU has turbo mode. The mode is 2.5 times faster than the default run mode. Activating the mode early significantly speeds up boot process. Signed-off-by: Sergey Yanovich <ynvich@gmail.com>
* | | arm: da830: moved pinmux configurations to the arch treeVishwanathrao Badarkhe, Manish2013-06-10-0/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move pinmux configurations for the DA830 SoCs from board file to the arch tree so that it can be used for all da830 based devices. Also, avoids duplicate pinmuxing in case of NAND. Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Christian Riesch <christian.riesch@omicron.at>
* | | OMAP5: Enable access to auxclk registersLubomir Popov2013-06-10-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | auxclk0 and auxclk1 are utilized on some OMAP5 boards. Define the infrastructure needed for accessing them without using magic numbers. Also remove unrelated TPS62361 defines from clocks.h Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
* | | arm: Remove OMAP2420H4 and all omap24xx supportTom Rini2013-06-10-18/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time. Signed-off-by: Tom Rini <trini@ti.com>
* | | ARM: DRA7xx: EMIF: Change settings required for EVM boardSricharan R2013-06-10-24/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DRA7 EVM board has the below configuration. Adding the settings for the same here. 2Gb_1_35V_DDR3L part * 2 on EMIF1 2Gb_1_35V_DDR3L part * 4 on EMIF2 Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: DRA7xx: clocks: Update PLL valuesLokesh Vutla2013-06-10-43/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>
* | | ARM: DRA7xx: Correct the SYS_CLK to 20MHZSricharan R2013-06-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. And also moving V_SCLK, V_OSCK defines to arch/clock.h for OMAP4+ boards. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc'sLokesh Vutla2013-06-10-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Slew rate compensation cells are not present for DRA7xx Soc's. So return from function srcomp_enable() if soc is not OMAP54xx. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: OMAP5: DRA7xx: support class 0 optimized voltagesNishanth Menon2013-06-10-12/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DRA752 now uses AVS Class 0 voltages which are voltages in efuse. This means that we can now use the optimized voltages which are stored as mV values in efuse and program PMIC accordingly. This allows us to go with higher OPP as needed in the system without the need for implementing complex AVS logic. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: DRA7xx: clocks: Fixing i2c_init for PMICLokesh Vutla2013-06-10-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | In DRA7xx Soc's voltage scaling is done using GPI2C. So i2c_init should happen before scaling. I2C driver uses __udelay which needs timer to be initialized. So moving timer_init just before voltage scaling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: DRA7xx: power Add support for tps659038 PMICLokesh Vutla2013-06-10-1/+60
| | | | | | | | | | | | | | | | | | | | | | | | TPS659038 is the power IC used in DRA7XX boards. Adding support for this and also adding pmic data for DRA7XX boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: OMAP4+: pmic: Make generic bus init and write functionsLokesh Vutla2013-06-10-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Voltage scaling can be done in two ways: -> Using SR I2C -> Using GP I2C In order to support both, have a function pointer in pmic_data so that we can call as per our requirement. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.hLokesh Vutla2013-06-10-6/+6
| | | | | | | | | | | | | | | | | | | | | To be consistent with other ARM platforms, renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: OMAP5: clocks: Do not enable sgx clocksSricharan R2013-06-10-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | SGX clocks should be enabled only for OMAP5 ES1.0. So this can be removed. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: OMAP4+: Cleanup header filesLokesh Vutla2013-06-10-0/+5
| | | | | | | | | | | | | | | | | | | | | After having the u-boot clean up series, there are many definitions that are unused in header files. Removing all those unused ones. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | OMAP5: Fix bug in omap5_es1_prcm structLubomir Popov2013-06-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newly introduced function setup_warmreset_time(), called from within prcm_init(), tries to write to the prm_rsttime OMAP5 register. The struct member holding this register's address is however initialized for OMAP5 ES2.0 only. On ES1.0 devices this uninitialized value causes a second (warm) reset at startup. Add .prm_rsttime address init to the ES1.0 struct. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com> Acked-by: Tom Rini <trini@ti.com>
* | | OMAP5: add ABB setup for MPU voltage domainAndrii Tseglytskyi2013-06-10-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | Patch adds a call of abb_setup() function, and proper registers definitions needed for ABB setup sequence. ABB is initialized for MPU voltage domain. Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
* | | OMAP3+: introduce generic ABB supportAndrii Tseglytskyi2013-06-10-0/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adaptive Body Biasing (ABB) modulates transistor bias voltages dynamically in order to optimize switching speed versus leakage. Adaptive Body-Bias ldos are present for some voltage domains starting with OMAP3630. There are three modes of operation: * Bypass - the default, it just follows the vdd voltage * Foward Body-Bias - applies voltage bias to increase transistor performance at the cost of power. Used to operate safely at high OPPs. * Reverse Body-Bias - applies voltage bias to decrease leakage and save power. Used to save power at lower OPPs. Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
* | | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-06-08-3/+491
|\ \ \ | | |/ | |/| | | | | | | Conflicts: drivers/serial/Makefile
| * | arm: mxs: Fix vectoring table craftingMarek Vasut2013-06-03-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vectoring table has to be placed at 0x0, but U-Boot on MX23/MX28 starts from RAM, so the vectoring table at 0x0 is not present. Craft code that will be placed at 0x0 and will redirect interrupt vectoring to proper location of the U-Boot in RAM. Signed-off-by: Marek Vasut <marex@denx.de> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | arm: vf610: Add Vybrid VF610 CPU supportAlison Wang2013-06-03-0/+469
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds generic codes to support Freescale's Vybrid VF610 CPU. It aligns Vybrid VF610 platform with i.MX platform. As there are some differences between VF610 and i.MX platforms, the specific codes are in the arch/arm/cpu/armv7/vf610 directory. Signed-off-by: Alison Wang <b18965@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* | | ARM: tegra: only enable SCU on Tegra20Tom Warren2013-06-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The non-SPL build of U-Boot on Tegra only runs on a single CPU, and hence there is no need to enable the SCU when running U-Boot. If an SMP OS is booted, and it needs the SCU enabled, it will enable the SCU itself. U-Boot doing so is redundant. The one exception is Tegra20, where an enabled SCU is required for some aspects of PCIe to work correctly. Some Tegra SoCs contain CPUs without a software-controlled SCU. In this case, attempting to turn it on actively causes problems. This is the case for Tegra114. For example, when running Linux, the first (or at least some very early) user-space process will trigger the following kernel message: Unhandled fault: imprecise external abort (0x406) at 0x00000000 This is typically accompanied by that process receving a fatal signal, and exiting. Since this process is usually pid 1, this causes total system boot failure. Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, fleshed out description, ported to upstream chipid APIs] Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.cTom Rini2013-06-05-36/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to call the save_omap_boot_params function on am33xx/ti81xx and other newer TI SoCs, so move the function to boot-common. Only OMAP4+ has the omap_hw_init_context function so add ifdefs to not call it on am33xx/ti81xx. Call save_omap_boot_params from s_init on am33xx/ti81xx boards. Reviewed-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* | | omap-common/hwinit-common.c: Mark omap_rev_string as staticTom Rini2013-06-04-1/+1
| | | | | | | | | | | | | | | | | | Only called in this file, mark as static. Signed-off-by: Tom Rini <trini@ti.com>
* | | arm: factorize relocate_code routineAlbert ARIBAUD2013-05-30-992/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace all relocate_code routines from ARM start.S files with a single instance in file arch/arm/lib/relocate.S. For PXA, this requires moving the dcache unlocking code from within relocate_code into c_runtime_cpu_setup. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Simon Glass <sjg@chromium.org>
* | | arm: do not compile relocate_code() for SPL buildsAlbert ARIBAUD2013-05-30-81/+55
| | | | | | | | | | | | | | | | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Simon Glass <sjg@chromium.org>
* | | tegra: Define CONFIG_SKIP_LOWLEVEL_INIT for SPL buildAxel Lin2013-05-28-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Then we can get rid of the #ifdef CONFIG_TEGRA guard in cpu_init_crit. Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | ARM: arm720t: Add missing CONFIG_SKIP_LOWLEVEL_INIT guard for cpu_init_critAxel Lin2013-05-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | cpu_init_crit() can be skipped, but the code is still enabled requiring a platform to supply lowlevel_init(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | ARM: tegra: support SKU 7 of Tegra20Stephen Warren2013-05-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make U-Boot aware of the Tegra20 SKU 7, and treat it identically to any other Tegra20. My Whistler board has a SoC with this SKU. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | ARM: tegra: support SKU 1 of Tegra114Stephen Warren2013-05-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make U-Boot aware of the Tegra114 SKU 1, and treat it identically to any other Tegra114. This value is used on (at least some) Dalmore boards with a production rather than engineering chip. Such boards are in the hands of some partners who want to use upstream U-Boot. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | Tegra: clk: always use find_best_divider() for periph clocksAllen Martin2013-05-28-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When adjusting peripheral clocks always use find_best_divider() instead of clk_get_divider() even when a secondary divider is not available. In the case where is requested clock is too slow to be derived from the parent clock this allows a best effort to get close to the requested clock. This comes up for commands like "sf" where the user can pass a clock speed on the command line or "sspi" where the clock is hardcoded to 1MHz, but the Tegra114 SPI controller can't go that low. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | arm: Enable -ffunction-sections / -fdata-sections / --gc-sectionsTom Rini2013-05-23-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | While other architectures have enabled these gcc / ld options for some time on U-Boot itself, ARM has only been doing this on SPL. Enable this on full U-Boot as well now. Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@ti.com>
* | | ARM: atmel: add sama5d3xek supportBo Shen2013-05-21-0/+649
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | Add sama5d3xek support with following feature - boot from NAND flash, PMECC support, 4bit ECC @ 512 bytes sector - boot from SPI flash support - boot from SD card support - LCD support - EMAC support - USB OHCI support Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | arm: at91: enable mci support for at91sam9g20ek.Wu, Josh2013-05-12-0/+4
| | | | | | | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | arm: at91: add at91sam9n12ek board supportWu, Josh2013-05-12-2/+180
|/ | | | | | | | | | | | Add support for following features: - nand boot, with PMECC 2bit ECC for 512 bytes sector - SPI flash boot - SD card boot - LCD support Signed-off-by: Josh Wu <josh.wu@atmel.com> [fix -Wimplicit-function-declaration for at91_lcd_hw_init()] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-91/+234
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| * ARM: OMAP: Add arch_cpu_init functionSRICHARAN R2013-05-10-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | The boot parameters passed from SPL to UBOOT must be saved as a part of uboot's gd data as early as possible, before we will inadvertently overwrite it. So adding a arch_cpu_init for the required Socs to save it. Signed-off-by: Sricharan R <r.sricharan@ti.com> [trini: Add igep0033 hunk] Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: OMAP: Cleanup boot parameters usageSRICHARAN R2013-05-10-66/+23
| | | | | | | | | | | | | | | | | | | | | | The boot parameters are read from individual variables assigned for each of them. This been corrected and now they are stored as a part of the global data 'gd' structure. So read them from 'gd' instead. Signed-off-by: Sricharan R <r.sricharan@ti.com> [trini: Add igep0033 hunk] Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: OMAP: Correct save_boot_params and replace with 'C' functionSRICHARAN R2013-05-10-6/+44
| | | | | | | | | | | | | | | | | | | | | | Currently save_boot_params saves the boot parameters passed from romcode. But this is not stored in a writable location consistently. So the current code would not work for a 'XIP' boot. Change this by saving the boot parameters in 'gd' which is always writable. Also add a 'C' function instead of an assembly code that is more readable. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines commonSRICHARAN R2013-05-10-8/+10
| | | | | | | | | | | | | | | | These defines are same across OMAP4/5. So move them to omap_common.h. This is required for the patches that follow. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * am33xx: Fix warning with CONFIG_DISPLAY_CPUINFOTom Rini2013-05-10-5/+1
| | | | | | | | | | | | | | | | The arm_freq and ddr_freq variables are unused, so remove. Fixup whitespace slightly while in here. Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Tom Rini <trini@ti.com>
| * da850: provide davinci_enable_uart0Eric Benard2013-05-10-0/+8
| | | | | | | | | | | | | | | | this is needed to bring UART0 out of reset but this function currently only exists for dm644x/355/365/646x when da850 (at least am1808 also need it). Signed-off-by: Eric Bénard <eric@eukrea.com>
| * ARM: OMAP5: Fix warm reset with USB cable connectedLokesh Vutla2013-05-10-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Warm reset on OMAP5 freezes when USB cable is connected. Fix requires PRM_RSTTIME.RSTTIME1 to be programmed with the time for which reset should be held low for the voltages and the oscillator to reach stable state. There are 3 parameters to be considered for calculating the time, which are mostly board and PMIC dependent. -1- Time taken by the Oscillator to shut + restart -2- PMIC OTP times -3- Voltage rail ramp times, which inturn depends on the PMIC slew rate and value of the voltage ramp needed. In order to keep the code in u-boot simple, have a way for boards to specify a pre computed time directly using the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' option. If boards fail to specify the time, use a default as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead. Using the default value translates into some ~22ms and should work in all cases. However in order to avoid this large delay hiding other bugs, its recommended that all boards look at their respective data sheets and specify a pre computed and optimal value using 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' In order to help future board additions to compute this config option value, add a README at doc/README.omap-reset-time which explains how to compute the value. Also update the toplevel README with the additional option and pointers to doc/README.omap-reset-time. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [rnayak@ti.com: Updated changelog and added the README] Signed-off-by: Rajendra Nayak <rnayak@ti.com>
| * OMAP5: USB: hsusbtll_clkctrl has to be in hw_auto for USB to workLubomir Popov2013-05-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | USB TLL clocks do not support 'explicit_en', only 'hw_auto' control (R. Sricharan). cm_l3init_hsusbtll_clkctrl has to be moved to the clk_modules_hw_auto_essential[] array in order to make the clock work. This fix is needed (but not sufficient) for USB EHCI operation in U-Boot. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
| * arm: omap: emif: Fix DDR3 init after warm resetLokesh Vutla2013-05-10-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EMIF supports a global warm reset mode, during which the EMIF keeps the SDRAM content. But if leveling is enabled at the time of warm reset for DDR3, the following steps needs to be done after warm reset: 1) Keep EMIF in self refresh mode. 2) Reset PHY to bring back the PHY to a known state. 3) Start Levelling procedure. Doing the same. And also enabling DLL lock and code output after warm reset. Tested on OMAP5432 ES2.0 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * OMAP5: I2C: Enable i2c5 clocksLubomir Popov2013-05-10-0/+1
| | | | | | | | | | | | | | I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. The i2c5 clock was however not enabled; do this here. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
generated by cgit v1.1 at 2024-10-31 20:28:17 +0000