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* | | | am33xx: Unused get_board_rev function removalPaul Kocialkowski2015-07-27-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All am33xx device tree are using device-tree, so get_board_rev is never actually called. Thus, we can get rid of it to make the code easier to maintain. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | omap3: CONFIG_REVISION_TAG ifdef check for get_board_revPaul Kocialkowski2015-07-27-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Despite being defined with __weak, this declaration of get_board_rev will conflict with the fallback one when ONFIG_REVISION_TAG is not defined. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | omap5: Definitions for SYS_BOOT-based fallback boot device selectionPaul Kocialkowski2015-07-27-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This introduces code to read the value of the SYS_BOOT pins on the OMAP5, as well as the memory-preferred scheme for the interpretation of each value. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | | | omap4: Definitions for SYS_BOOT-based fallback boot device selectionPaul Kocialkowski2015-07-27-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This introduces code to read the value of the SYS_BOOT pins on the OMAP4, as well as the memory-preferred scheme for the interpretation of each value. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | | | omap3: Definitions for SYS_BOOT-based fallback boot device selectionPaul Kocialkowski2015-07-27-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This introduces code to read the value of the SYS_BOOT pins on the OMAP3, as well as the memory-preferred scheme for the interpretation of each value. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | | | omap-common: SYS_BOOT-based fallback boot device selection for peripheral bootPaul Kocialkowski2015-07-27-7/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP devices might boot from peripheral devices, such as UART or USB. When that happens, the U-Boot SPL tries to boot the next stage (complete U-Boot) from that peripheral device, but in most cases, this is not a valid boot device. This introduces a fallback option that reads the SYS_BOOT pins, that are used by the bootrom to determine which device to boot from. It is intended for the SYS_BOOT value to be interpreted in the memory-preferred scheme, so that the U-Boot SPL can load the next stage from a valid location. Practically, this options allows loading the U-Boot SPL through USB and have it load the next stage according to the memory device selected by SYS_BOOT instead of stalling. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | | | omap-common: Boot device define instead of hardcoded valuePaul Kocialkowski2015-07-27-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that SPL boot devices are clearly defined, we can use BOOT_DEVICE_QSPI_4 instead of a hardcoded value. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | | | omap-common: Common boot code OMAP3 support and cleanupPaul Kocialkowski2015-07-27-124/+78
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This introduces OMAP3 support for the common omap boot code, as well as a major cleanup of the common omap boot code. First, the omap_boot_parameters structure becomes platform-specific, since its definition differs a bit across omap platforms. The offsets are removed as well since it is U-Boot's coding style to use structures for mapping such kind of data (in the sense that it is similar to registers). It is correct to assume that romcode structure encoding is the same as U-Boot, given the description of these structures in the TRMs. The original address provided by the bootrom is passed to the U-Boot binary instead of a duplicate of the structure stored in global data. This allows to have only the relevant (boot device and mode) information stored in global data. It is also expected that the address where the bootrom stores that information is not overridden by the U-Boot SPL or U-Boot. The save_omap_boot_params is expected to handle all special cases where the data provided by the bootrom cannot be used as-is, so that spl_boot_device and spl_boot_mode only return the data from global data. All of this is only relevant when the U-Boot SPL is used. In cases it is not, save_boot_params should fallback to its weak (or board-specific) definition. save_omap_boot_params should not be called in that context either. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-07-25-15/+75
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| * | | sunxi: musb: Stop treating not having a vbus-det gpio as an errorHans de Goede2015-07-25-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some boards the otg is wired up in host-only mode in this case we have no vbus-det gpio. Stop logging an error from sunxi_usb_phy_vbus_detect() in this case, and stop treating sunxi_usb_phy_vbus_detect() returning a negative errno, as if a charger is plugged into the otg port. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: usb-phy: Add support for reading otg id pin valueHans de Goede2015-07-25-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for reading the id pin value of the otg connector to the usb phy code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: spl: Detect at runtime where SPL was read fromDaniel Kochmański2015-07-24-12/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make possible using a single `u-boot-sunxi-with-spl.bin` binary for both NAND memory and SD card. Detection where SPL was read from is implemented in `spl_boot_device`. Signed-off-by: Daniel Kochmański <dkochmanski@turtle-solutions.eu> CC: Roy Spliet <r.spliet@ultimaker.com> Cc: Ian Campbell <ijc@hellion.org.uk> [hdegoede@redhat.com: Some small coding style fixes] Acked-by: Hans De Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | | Merge git://git.denx.de/u-boot-usbTom Rini2015-07-24-1/+1
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| * | | usb: Fastboot function config for better consistency with other functionsPaul Kocialkowski2015-07-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB download gadget functions such as thor and dfu have a separate config option for the USB gadget part of the code, independent from the command part. This switches the fastboot USB gadget to the same scheme, for better consistency. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
* | | | dm: arm: Put driver model I2C drivers before legacy onesSimon Glass2015-07-21-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Driver-model I2C drivers can be picked up by the linker script rule for legacy drivers. Change the order to avoid this. We could make the legacy code depend on !CONFIG_DM_I2C but that is not necessary and it is good to keep conditions to a minimum. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | dm: Reduce SPL device tree sizeSimon Glass2015-07-21-1/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | The SPL device tree size must be minimised to save memory. Only include properties that are needed by SPL - this is determined by the presence of the "u-boot,dm-pre-reloc" property. Also remove a predefined list of unused properties from the nodes that remain. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup.Zhichun Hua2015-07-20-15/+8
| | | | | | | | | | | | | | | | | | | | | | | | When final MMU table is setup in DDR, TCR attributes must match those of the memroy for cacheability and shareability. Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* | | armv8/ls2085a: Enable DSPI get input clk form 'mxc_get_clock'Haikun Wang2015-07-20-0/+2
| | | | | | | | | | | | | | | Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | arm/ls102xa: Add PSCI support for ls102xaWang Dongsheng2015-07-20-0/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform. Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.SWang Dongsheng2015-07-20-40/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | arm: ls1021a: Remove the inappropriate use of the function 'sprintf'Alison Wang2015-07-20-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the function 'sprintf' does not check buffer boundaries but outputs to the buffer 'enet' of fixed size (16), this patch removes the function 'sprintf', and uses 'strcpy' instead. It will assign the character arrays 'enet' and 'phy' the corresponding character strings. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | armv8/fsl-lsch3: device tree fixups for PCI stream IDsStuart Yoder2015-07-20-0/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the infrastructure to update device tree nodes to convey SMMU stream IDs in the device tree. Fixups are implemented for PCI controllers initially. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | arm/errata: Update required bits for A57 cores erratasBhupesh Sharma2015-07-20-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the setting of required bits for A57 cores erratas - 828024 and 826974 Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Dai Haruki <dai.haruki at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | armv8/ls2085a: Update SoC README for DDR layoutPrabhakar Kushwaha2015-07-20-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update SoC README to provide details of - Memory regions - Memory used by MC and Debug server Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | armv8/fsl-ch3: Add support to print SoC personalityPrabhakar Kushwaha2015-07-20-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to print out the SoC personality. Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | armv8/fsl-lsch3: Fix DDR speed messageYork Sun2015-07-20-2/+2
| | | | | | | | | | | | | | | | | | | | | DDR speed should be in MT/s, not MHz. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
* | | armv8/ls2085a: call ft_pcie_setup() to change dts statusPrabhakar Kushwaha2015-07-20-0/+4
| |/ |/| | | | | | | | | | | | | | | call ft_pci_setup() to disable PCIe dts node if corresponding PCIe controller is disabled according to RCW Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-07-14-1/+8
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| * stv0991: configure clock & pad muxing for qspiVikas Manocha2015-07-03-1/+8
| | | | | | | | | | | | | | | | stv0991 has cadence qspi controller for flash interfacing, this patch configures the device pads & clock for the controller. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2015-07-07-4/+3
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| * \ Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-07-07-122/+674
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| * | armv7: better comment in start.SPavel Machek2015-07-07-4/+3
| | | | | | | | | | | | | | | | | | | | | Fix big/small letters in comment. Signed-off-by: Pavel Machek <pavel@denx.de> Tested-by: Marek Vasut <marex@denx.de>
* | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-07-05-6/+11
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| * | | sunxi: Add support for UART0 in PB pin group on A33Chen-Yu Tsai2015-07-05-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A33 adds a pinmux function for UART0 in the PB pin group. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: rsb: Enable R_PIO clock before configuring external pinsChen-Yu Tsai2015-07-05-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original code was configuring the external pins after enabling the R_PIO clock, which meant the configuration never made it to the pin controller the first time in SPL. Why this was working before is uncertain. Maybe the state was left from a previous boot sequence, or RSB just happened to be the default configuration. However with some A33 chips, SPL failed to configure the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev board. Reordering the calls fixed this. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: hardware-feature-specific function index defines for PORT F UART0Chen-Yu Tsai2015-07-05-4/+4
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | Commit 487b327 ("sunxi: GPIO pin mux hardware-feature-specific function index defines") renamed all GPIO index defines, but missed the PORT F UART0 setup functions. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-07-03-1/+8
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: configs/tbs2910_defconfig configs/tqma6q_mba6_mmc_defconfig configs/tqma6q_mba6_spi_defconfig configs/tqma6s_mba6_mmc_defconfig configs/tqma6s_mba6_spi_defconfig include/configs/mx6_common.h Signed-off-by: Tom Rini <trini@konsulko.com>
| * | imx: mx6 correct get_cpu_revPeng Fan2015-06-27-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DIGPROG register map: 23 ------- 16 | 15 ------ 8 | 7 --- 0 | Major upper | Major Lower | Minor | We also need to account for Major Lower. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | arm: mx6: tqma6: CPU type selection via KconfigMarkus Niebel2015-06-27-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the first patch to remove the CONFIG_SYS_EXTRA_OPTIONS. This patch implements CPU type selection from Kconfig. Further Kconfig stuff is added later. Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
* | | Revert "sunxi/nand: Add support to the SPL for loading u-boot from internal ↵Ian Campbell2015-06-28-12/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NAND memory" This reverts commit f76eba38b3eda905ff3bdc18dd1240d3dcbc6e5a. This patch did not have a full and proper copyright/S-o-b chain. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Conflicts: include/configs/sun6i.h include/configs/sun8i.h
* | | Move default y configs out of arch/board KconfigJoe Hershberger2015-06-25-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some archs/boards specify their own default by pre-defining the config which causes the Kconfig system to mix up the order of the configs in the defconfigs... This will cause merge pain if allowed to proliferate. Remove the configs that behave this way from the archs. A few configs still remain, but that is because they only exist as defaults and do not have a proper Kconfig entry. Those appear to be: SPIFLASH DISPLAY_BOARDINFO Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> [trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates, drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM] Signed-off-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7: Change configuration to prevent DDR reset control from EMIFNishanth Menon2015-06-19-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DRA7/AM57xx devices can be operated in many different configurations. When the SoC is supposed to support a configuration where low power mode state may involve the SoC completely powered off and DDR is in self refresh, SoC EMIF controller should not be the master of the reset signal and an external entity might be in control of things. The default configuration of Linux on TI evms involve not powering off the voltage rails (due to various reasons including reliability concerns) and must not allow DDR reset to be controlled by EMIF. On platforms where external entity might control the reset signal, this configuration will be a "dont care". Fixes: 536d87470869 ("ARM: DRA7: Update DDR IO registers") Tested-by: Keerthy <j-keerthy@ti.com> Acked-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | sun6i: cpu_reset: Do not return from cpu_reset()Hans de Goede2015-06-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently on sun6i after a "reset" the prompt returns and the user can even type stuff until the watchdog triggers and does the actual reset. This is somewhat unexpected behavior for the "reset" command, this commit adds an endless loop to wait for the watchdog to trigger so that we do not return to the prompt. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | ARM: DRA7: emif: Fix DDR init sequence during warm resetLokesh Vutla2015-06-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after warm reset, emif needs to be configured to bring it back to a known state. So configure EMIF during warm reset. Reported-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | am33xx: Re-enable SW levelling for DDR2Tom Rini2015-06-15-34/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The recent changes for hw leveling on am33xx were not intended for DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config value to check against. This lets us pass in the value we would use to configure, when we have not yet configured the board yet. In other cases update the call to be as functional as before and check an already programmed value in. Tested-by: Yan Liu <yan-liu@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: BeagleBoard-x15: Enable i2c5 clocksLokesh Vutla2015-06-15-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | On AM57xx evm I2C5 is used to detect the LCD board by reading the EEPROM present on the bus. Enable i2c5 clocks to help that. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7: Add support for manual mode configurationLokesh Vutla2015-06-12-1/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to the regular mux configuration, certain pins of DRA7 require to have "manual mode" also programmed, when predefined delay characteristics cannot be used for the interface. struct iodelay_cfg_entry is introduced for populating manual mode IO timings. For configuring manual mode, along with the normal pad configuration do the following steps: - Select MODESELECT field of each assocaited PAD. CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux) - Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL. And pass the offset of the CFG_XXX register in iodelay_cfg_entry. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7: Add support for IO delay configurationLokesh Vutla2015-06-12-0/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On DRA7, in addition to the regular muxing of pins, an additional hardware module called IODelay which is also expected to be configured. This "IODelay" module has it's own register space that is independent of the control module. It is advocated strongly in TI's official documentation considering the existing design of the DRA7 family of processors during mux or IODelay recalibration, there is a potential for a significant glitch which may cause functional impairment to certain hardware. It is hence recommended to do muxing as part of IOdelay recalibration. IODELAY recalibration sequence: - Complete AVS voltage change on VDD_CORE_L - Unlock IODLAY config registers. - Perform IO delay calibration with predefined values. - Isolate all the IOs - Update the delay mechanism for each IO with new calibrated values. - Configure PAD configuration registers - De-isolate all the IOs. - Relock IODELAY config registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7: Make do_set_mux32() genericLokesh Vutla2015-06-12-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | do_set_mux32() is redefined in dra7xx and beagle_x15 boards. IO delay recalibration sequence also needs this. Making it generic to avoid duplication. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL registerLokesh Vutla2015-06-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | When DLL_CALIB_INTERVAL is set, an extra delay is added which is not required and it consumes EMIF bandwidth. So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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